1757 				    SISLANDS_SMC_SCLK_VALUE *sclk);
2321 		prev_sclk = state->performance_levels[i-1].sclk;  in si_populate_power_containment_values()
2322 		max_sclk  = state->performance_levels[i].sclk;  in si_populate_power_containment_values()
2341 		if (min_sclk < state->performance_levels[0].sclk)  in si_populate_power_containment_values()
2342 			min_sclk = state->performance_levels[0].sclk;  in si_populate_power_containment_values()
2416 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in si_populate_sq_ramping_values()
2851 	u32 sclk = 0;  in si_init_smc_spll_table()  local
2864 		ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);  in si_init_smc_spll_table()
2897 		sclk += 512;  in si_init_smc_spll_table()
2943 	u32 mclk, sclk;  in si_apply_state_adjust_rules()  local
2985 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in si_apply_state_adjust_rules()
2986 				ps->performance_levels[i].sclk = max_limits->sclk;  in si_apply_state_adjust_rules()
3004 			if (ps->performance_levels[i].sclk > max_sclk_vddc)  in si_apply_state_adjust_rules()
3005 				ps->performance_levels[i].sclk = max_sclk_vddc;  in si_apply_state_adjust_rules()
3020 			if (ps->performance_levels[i].sclk > max_sclk)  in si_apply_state_adjust_rules()
3021 				ps->performance_levels[i].sclk = max_sclk;  in si_apply_state_adjust_rules()
3036 		sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;  in si_apply_state_adjust_rules()
3039 		sclk = ps->performance_levels[0].sclk;  in si_apply_state_adjust_rules()
3044 	ps->performance_levels[0].sclk = sclk;  in si_apply_state_adjust_rules()
3050 		sclk = ps->performance_levels[0].sclk;  in si_apply_state_adjust_rules()
3052 			if (sclk < ps->performance_levels[i].sclk)  in si_apply_state_adjust_rules()
3053 				sclk = ps->performance_levels[i].sclk;  in si_apply_state_adjust_rules()
3056 			ps->performance_levels[i].sclk = sclk;  in si_apply_state_adjust_rules()
3061 			if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)  in si_apply_state_adjust_rules()
3062 				ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;  in si_apply_state_adjust_rules()
3093 						   ps->performance_levels[i].sclk,  in si_apply_state_adjust_rules()
4149 					    u16 voltage, u32 sclk, u32 mclk,  in si_populate_phase_shedding_value()  argument
4156 		    (sclk <= limits->entries[i].sclk) &&  in si_populate_phase_shedding_value()
4240 		(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);  in si_populate_memory_timing_parameters()
4243 					    pl->sclk,  in si_populate_memory_timing_parameters()
4337 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =  in si_populate_smc_initial_state()
4339 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =  in si_populate_smc_initial_state()
4341 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =  in si_populate_smc_initial_state()
4343 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =  in si_populate_smc_initial_state()
4345 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =  in si_populate_smc_initial_state()
4347 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =  in si_populate_smc_initial_state()
4350 	table->initialState.levels[0].sclk.sclk_value =  in si_populate_smc_initial_state()
4351 		cpu_to_be32(initial_state->performance_levels[0].sclk);  in si_populate_smc_initial_state()
4384 						 initial_state->performance_levels[0].sclk,  in si_populate_smc_initial_state()
4536 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =  in si_populate_smc_acpi_state()
4538 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =  in si_populate_smc_acpi_state()
4540 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =  in si_populate_smc_acpi_state()
4542 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =  in si_populate_smc_acpi_state()
4546 	table->ACPIState.levels[0].sclk.sclk_value = 0;  in si_populate_smc_acpi_state()
4722 				    SISLANDS_SMC_SCLK_VALUE *sclk)  in si_calculate_sclk_params()  argument
4779 	sclk->sclk_value = engine_clock;  in si_calculate_sclk_params()
4780 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;  in si_calculate_sclk_params()
4781 	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;  in si_calculate_sclk_params()
4782 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;  in si_calculate_sclk_params()
4783 	sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;  in si_calculate_sclk_params()
4784 	sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;  in si_calculate_sclk_params()
4785 	sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;  in si_calculate_sclk_params()
4792 				  SISLANDS_SMC_SCLK_VALUE *sclk)  in si_populate_sclk_value()  argument
4799 		sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);  in si_populate_sclk_value()
4800 		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);  in si_populate_sclk_value()
4801 		sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);  in si_populate_sclk_value()
4802 		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);  in si_populate_sclk_value()
4803 		sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);  in si_populate_sclk_value()
4804 		sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);  in si_populate_sclk_value()
4805 		sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);  in si_populate_sclk_value()
4933 	ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);  in si_convert_power_level_to_smc()
4976 				     pl->sclk,  in si_convert_power_level_to_smc()
5010 						       pl->sclk,  in si_convert_power_level_to_smc()
5050 			state->performance_levels[i + 1].sclk,  in si_populate_smc_t()
5051 			state->performance_levels[i].sclk,  in si_populate_smc_t()
5142 	threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;  in si_convert_power_state_to_smc()
5176 				(state->performance_levels[i].sclk < threshold) ?  in si_convert_power_state_to_smc()
6666 	pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);  in si_parse_pplib_clock_info()
6667 	pl->sclk |= clock_info->si.ucEngineClockHigh << 16;  in si_parse_pplib_clock_info()
6713 		pl->sclk = rdev->clock.default_sclk;  in si_parse_pplib_clock_info()
6721 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in si_parse_pplib_clock_info()
6959 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in si_dpm_init()
6999 			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);  in si_dpm_debugfs_print_current_performance_level()
7017 		return pl->sclk;  in si_dpm_get_current_sclk()