364 	u32 value;  in trinity_gfx_powergating_initialize()  local
376 	value = RREG32_SMC(GFX_POWER_GATING_CNTL);  in trinity_gfx_powergating_initialize()
377 	value &= ~(SSSD_MASK | PDS_DIV_MASK);  in trinity_gfx_powergating_initialize()
379 		value |= SSSD(1);  in trinity_gfx_powergating_initialize()
380 	value |= PDS_DIV(dividers.post_div);  in trinity_gfx_powergating_initialize()
381 	WREG32_SMC(GFX_POWER_GATING_CNTL, value);  in trinity_gfx_powergating_initialize()
517 	u32 value;  in trinity_gfx_dynamic_mgpg_enable()  local
520 		value = RREG32_SMC(PM_I_CNTL_1);  in trinity_gfx_dynamic_mgpg_enable()
521 		value &= ~DS_PG_CNTL_MASK;  in trinity_gfx_dynamic_mgpg_enable()
522 		value |= DS_PG_CNTL(1);  in trinity_gfx_dynamic_mgpg_enable()
523 		WREG32_SMC(PM_I_CNTL_1, value);  in trinity_gfx_dynamic_mgpg_enable()
525 		value = RREG32_SMC(SMU_S_PG_CNTL);  in trinity_gfx_dynamic_mgpg_enable()
526 		value &= ~DS_PG_EN_MASK;  in trinity_gfx_dynamic_mgpg_enable()
527 		value |= DS_PG_EN(1);  in trinity_gfx_dynamic_mgpg_enable()
528 		WREG32_SMC(SMU_S_PG_CNTL, value);  in trinity_gfx_dynamic_mgpg_enable()
530 		value = RREG32_SMC(SMU_S_PG_CNTL);  in trinity_gfx_dynamic_mgpg_enable()
531 		value &= ~DS_PG_EN_MASK;  in trinity_gfx_dynamic_mgpg_enable()
532 		WREG32_SMC(SMU_S_PG_CNTL, value);  in trinity_gfx_dynamic_mgpg_enable()
534 		value = RREG32_SMC(PM_I_CNTL_1);  in trinity_gfx_dynamic_mgpg_enable()
535 		value &= ~DS_PG_CNTL_MASK;  in trinity_gfx_dynamic_mgpg_enable()
536 		WREG32_SMC(PM_I_CNTL_1, value);  in trinity_gfx_dynamic_mgpg_enable()
586 	u32 value;  in trinity_set_divider_value()  local
594 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_divider_value()
595 	value &= ~CLK_DIVIDER_MASK;  in trinity_set_divider_value()
596 	value |= CLK_DIVIDER(dividers.post_div);  in trinity_set_divider_value()
597 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_set_divider_value()
604 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);  in trinity_set_divider_value()
605 	value &= ~PD_SCLK_DIVIDER_MASK;  in trinity_set_divider_value()
606 	value |= PD_SCLK_DIVIDER(dividers.post_div);  in trinity_set_divider_value()
607 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);  in trinity_set_divider_value()
613 	u32 value;  in trinity_set_ds_dividers()  local
616 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_ds_dividers()
617 	value &= ~DS_DIV_MASK;  in trinity_set_ds_dividers()
618 	value |= DS_DIV(divider);  in trinity_set_ds_dividers()
619 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_ds_dividers()
625 	u32 value;  in trinity_set_ss_dividers()  local
628 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_ss_dividers()
629 	value &= ~DS_SH_DIV_MASK;  in trinity_set_ss_dividers()
630 	value |= DS_SH_DIV(divider);  in trinity_set_ss_dividers()
631 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_ss_dividers()
638 	u32 value;  in trinity_set_vid()  local
641 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_vid()
642 	value &= ~VID_MASK;  in trinity_set_vid()
643 	value |= VID(vid_7bit);  in trinity_set_vid()
644 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_set_vid()
646 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_vid()
647 	value &= ~LVRT_MASK;  in trinity_set_vid()
648 	value |= LVRT(0);  in trinity_set_vid()
649 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_set_vid()
655 	u32 value;  in trinity_set_allos_gnb_slow()  local
658 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);  in trinity_set_allos_gnb_slow()
659 	value &= ~GNB_SLOW_MASK;  in trinity_set_allos_gnb_slow()
660 	value |= GNB_SLOW(gnb_slow);  in trinity_set_allos_gnb_slow()
661 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);  in trinity_set_allos_gnb_slow()
667 	u32 value;  in trinity_set_force_nbp_state()  local
670 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);  in trinity_set_force_nbp_state()
671 	value &= ~FORCE_NBPS1_MASK;  in trinity_set_force_nbp_state()
672 	value |= FORCE_NBPS1(force_nbp_state);  in trinity_set_force_nbp_state()
673 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);  in trinity_set_force_nbp_state()
679 	u32 value;  in trinity_set_display_wm()  local
682 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_display_wm()
683 	value &= ~DISPLAY_WM_MASK;  in trinity_set_display_wm()
684 	value |= DISPLAY_WM(wm);  in trinity_set_display_wm()
685 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_display_wm()
691 	u32 value;  in trinity_set_vce_wm()  local
694 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_vce_wm()
695 	value &= ~VCE_WM_MASK;  in trinity_set_vce_wm()
696 	value |= VCE_WM(wm);  in trinity_set_vce_wm()
697 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);  in trinity_set_vce_wm()
703 	u32 value;  in trinity_set_at()  local
706 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);  in trinity_set_at()
707 	value &= ~AT_MASK;  in trinity_set_at()
708 	value |= AT(at);  in trinity_set_at()
709 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);  in trinity_set_at()
734 	u32 value;  in trinity_power_level_enable_disable()  local
737 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_power_level_enable_disable()
738 	value &= ~STATE_VALID_MASK;  in trinity_power_level_enable_disable()
740 		value |= STATE_VALID(1);  in trinity_power_level_enable_disable()
741 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);  in trinity_power_level_enable_disable()
754 	u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);  in trinity_start_dpm()  local
756 	value &= ~(SCLK_DPM_EN_MASK | SCLK_DPM_BOOT_STATE_MASK | VOLTAGE_CHG_EN_MASK);  in trinity_start_dpm()
757 	value |= SCLK_DPM_EN(1) | SCLK_DPM_BOOT_STATE(0) | VOLTAGE_CHG_EN(1);  in trinity_start_dpm()
758 	WREG32_SMC(SMU_SCLK_DPM_CNTL, value);  in trinity_start_dpm()
991 	u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);  in trinity_program_ttt()  local
993 	value &= ~(HT_MASK | LT_MASK);  in trinity_program_ttt()
994 	value |= HT((pi->thermal_auto_throttling + 49) * 8);  in trinity_program_ttt()
995 	value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8);  in trinity_program_ttt()
996 	WREG32_SMC(SMU_SCLK_DPM_TTT, value);  in trinity_program_ttt()
1001 	u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);  in trinity_enable_att()  local
1003 	value &= ~SCLK_TT_EN_MASK;  in trinity_enable_att()
1004 	value |= SCLK_TT_EN(1);  in trinity_enable_att()
1005 	WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value);  in trinity_enable_att()
1014 	u32 value;  in trinity_program_sclk_dpm()  local
1020 	value = RREG32_SMC(PM_I_CNTL_1);  in trinity_program_sclk_dpm()
1021 	value &= ~SCLK_DPM_MASK;  in trinity_program_sclk_dpm()
1022 	value |= SCLK_DPM(ni);  in trinity_program_sclk_dpm()
1023 	WREG32_SMC(PM_I_CNTL_1, value);  in trinity_program_sclk_dpm()