Lines Matching refs:writel
121 writel(1, vtg->regs + VTG_DRST_AUTOC); in vtg_reset()
132 writel(mode->htotal, vtg->regs + VTG_CLKLN); in vtg_set_mode()
133 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); in vtg_set_mode()
137 writel(tmp, vtg->regs + VTG_VID_TFO); in vtg_set_mode()
138 writel(tmp, vtg->regs + VTG_VID_BFO); in vtg_set_mode()
142 writel(tmp, vtg->regs + VTG_VID_TFS); in vtg_set_mode()
143 writel(tmp, vtg->regs + VTG_VID_BFS); in vtg_set_mode()
148 writel(tmp, vtg->regs + VTG_H_HD_1); in vtg_set_mode()
152 writel(tmp, vtg->regs + VTG_TOP_V_VD_1); in vtg_set_mode()
153 writel(tmp, vtg->regs + VTG_BOT_V_VD_1); in vtg_set_mode()
154 writel(0, vtg->regs + VTG_TOP_V_HD_1); in vtg_set_mode()
155 writel(0, vtg->regs + VTG_BOT_V_HD_1); in vtg_set_mode()
159 writel(tmp, vtg->regs + VTG_H_HD_2); in vtg_set_mode()
163 writel(tmp, vtg->regs + VTG_TOP_V_VD_2); in vtg_set_mode()
164 writel(tmp, vtg->regs + VTG_BOT_V_VD_2); in vtg_set_mode()
165 writel(0, vtg->regs + VTG_TOP_V_HD_2); in vtg_set_mode()
166 writel(0, vtg->regs + VTG_BOT_V_HD_2); in vtg_set_mode()
171 writel(tmp, vtg->regs + VTG_H_HD_3); in vtg_set_mode()
175 writel(tmp, vtg->regs + VTG_TOP_V_VD_3); in vtg_set_mode()
176 writel(tmp, vtg->regs + VTG_BOT_V_VD_3); in vtg_set_mode()
180 writel(tmp, vtg->regs + VTG_TOP_V_HD_3); in vtg_set_mode()
181 writel(tmp, vtg->regs + VTG_BOT_V_HD_3); in vtg_set_mode()
185 writel(tmp, vtg->regs + VTG_H_HD_4); in vtg_set_mode()
189 writel(tmp, vtg->regs + VTG_TOP_V_VD_4); in vtg_set_mode()
190 writel(tmp, vtg->regs + VTG_BOT_V_VD_4); in vtg_set_mode()
191 writel(0, vtg->regs + VTG_TOP_V_HD_4); in vtg_set_mode()
192 writel(0, vtg->regs + VTG_BOT_V_HD_4); in vtg_set_mode()
195 writel(type, vtg->regs + VTG_MODE); in vtg_set_mode()
201 writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR); in vtg_enable_irq()
202 writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR); in vtg_enable_irq()
203 writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET); in vtg_enable_irq()
300 writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR); in vtg_irq()