Lines Matching refs:dc
84 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
89 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_readl_active()
91 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
92 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
93 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
95 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_readl_active()
111 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
113 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
114 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
232 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, in tegra_dc_setup_window() argument
249 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_setup_window()
252 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_setup_window()
254 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
255 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
258 tegra_dc_writel(dc, value, DC_WIN_POSITION); in tegra_dc_setup_window()
261 tegra_dc_writel(dc, value, DC_WIN_SIZE); in tegra_dc_setup_window()
269 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); in tegra_dc_setup_window()
282 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); in tegra_dc_setup_window()
287 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); in tegra_dc_setup_window()
288 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); in tegra_dc_setup_window()
290 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); in tegra_dc_setup_window()
291 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); in tegra_dc_setup_window()
293 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
296 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
297 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
299 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
301 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
307 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); in tegra_dc_setup_window()
308 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); in tegra_dc_setup_window()
310 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
328 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); in tegra_dc_setup_window()
349 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); in tegra_dc_setup_window()
356 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); in tegra_dc_setup_window()
357 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); in tegra_dc_setup_window()
358 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); in tegra_dc_setup_window()
359 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); in tegra_dc_setup_window()
360 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); in tegra_dc_setup_window()
361 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); in tegra_dc_setup_window()
362 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); in tegra_dc_setup_window()
363 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); in tegra_dc_setup_window()
373 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_dc_setup_window()
379 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); in tegra_dc_setup_window()
380 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); in tegra_dc_setup_window()
384 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
385 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
386 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
390 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
391 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
396 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
397 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
402 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_setup_window()
511 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_atomic_check() local
528 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
556 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_plane_atomic_update() local
590 tegra_dc_setup_window(dc, p->index, &window); in tegra_plane_atomic_update()
597 struct tegra_dc *dc; in tegra_plane_atomic_disable() local
605 dc = to_tegra_dc(old_state->crtc); in tegra_plane_atomic_disable()
607 spin_lock_irqsave(&dc->lock, flags); in tegra_plane_atomic_disable()
610 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_plane_atomic_disable()
612 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); in tegra_plane_atomic_disable()
614 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_plane_atomic_disable()
616 spin_unlock_irqrestore(&dc->lock, flags); in tegra_plane_atomic_disable()
628 struct tegra_dc *dc) in tegra_dc_primary_plane_create() argument
706 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_cursor_atomic_update() local
738 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
742 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
746 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
748 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
750 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
757 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
761 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
768 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
775 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
777 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
779 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
800 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
821 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, in tegra_dc_cursor_plane_create()
867 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
884 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, in tegra_dc_overlay_plane_create()
897 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) in tegra_dc_add_planes() argument
903 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); in tegra_dc_add_planes()
911 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc) in tegra_dc_get_vblank_counter() argument
913 if (dc->syncpt) in tegra_dc_get_vblank_counter()
914 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
917 return drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
920 void tegra_dc_enable_vblank(struct tegra_dc *dc) in tegra_dc_enable_vblank() argument
924 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_enable_vblank()
926 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
928 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
930 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_enable_vblank()
933 void tegra_dc_disable_vblank(struct tegra_dc *dc) in tegra_dc_disable_vblank() argument
937 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_disable_vblank()
939 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
941 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
943 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_disable_vblank()
946 static void tegra_dc_finish_page_flip(struct tegra_dc *dc) in tegra_dc_finish_page_flip() argument
948 struct drm_device *drm = dc->base.dev; in tegra_dc_finish_page_flip()
949 struct drm_crtc *crtc = &dc->base; in tegra_dc_finish_page_flip()
955 if (!dc->event) { in tegra_dc_finish_page_flip()
962 spin_lock(&dc->lock); in tegra_dc_finish_page_flip()
965 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_finish_page_flip()
966 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
967 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); in tegra_dc_finish_page_flip()
968 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
970 spin_unlock(&dc->lock); in tegra_dc_finish_page_flip()
973 drm_crtc_send_vblank_event(crtc, dc->event); in tegra_dc_finish_page_flip()
975 dc->event = NULL; in tegra_dc_finish_page_flip()
983 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_cancel_page_flip() local
989 if (dc->event && dc->event->base.file_priv == file) { in tegra_dc_cancel_page_flip()
990 dc->event->base.destroy(&dc->event->base); in tegra_dc_cancel_page_flip()
992 dc->event = NULL; in tegra_dc_cancel_page_flip()
1055 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1060 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1062 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1064 tegra_dc_commit(dc); in tegra_dc_stop()
1067 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1071 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1076 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1081 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1087 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1093 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_disable() local
1096 if (!tegra_dc_idle(dc)) { in tegra_crtc_disable()
1097 tegra_dc_stop(dc); in tegra_crtc_disable()
1103 tegra_dc_wait_idle(dc, 100); in tegra_crtc_disable()
1122 if (dc->rgb) { in tegra_crtc_disable()
1123 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_disable()
1126 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_disable()
1139 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1146 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1149 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1153 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1157 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1161 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1164 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1181 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1188 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1198 static void tegra_dc_commit_state(struct tegra_dc *dc, in tegra_dc_commit_state() argument
1204 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1206 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1219 dev_err(dc->dev, in tegra_dc_commit_state()
1224 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1229 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_dc_commit_state()
1236 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_mode_set_nofb() local
1239 tegra_dc_commit_state(dc, state); in tegra_crtc_mode_set_nofb()
1242 tegra_dc_set_timings(dc, mode); in tegra_crtc_mode_set_nofb()
1245 if (dc->soc->supports_interlacing) { in tegra_crtc_mode_set_nofb()
1246 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_mode_set_nofb()
1248 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_mode_set_nofb()
1251 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_mode_set_nofb()
1254 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_mode_set_nofb()
1256 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_mode_set_nofb()
1259 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_mode_set_nofb()
1261 tegra_dc_commit(dc); in tegra_crtc_mode_set_nofb()
1282 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_begin() local
1289 dc->event = crtc->state->event; in tegra_crtc_atomic_begin()
1297 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
1299 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1300 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1316 struct tegra_dc *dc = data; in tegra_dc_irq() local
1319 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
1320 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
1332 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
1333 tegra_dc_finish_page_flip(dc); in tegra_dc_irq()
1348 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1352 tegra_dc_readl(dc, name)) in tegra_dc_show_regs()
1576 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) in tegra_dc_debugfs_init() argument
1582 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); in tegra_dc_debugfs_init()
1583 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); in tegra_dc_debugfs_init()
1586 if (!dc->debugfs) in tegra_dc_debugfs_init()
1589 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_debugfs_init()
1591 if (!dc->debugfs_files) { in tegra_dc_debugfs_init()
1597 dc->debugfs_files[i].data = dc; in tegra_dc_debugfs_init()
1599 err = drm_debugfs_create_files(dc->debugfs_files, in tegra_dc_debugfs_init()
1601 dc->debugfs, minor); in tegra_dc_debugfs_init()
1605 dc->minor = minor; in tegra_dc_debugfs_init()
1610 kfree(dc->debugfs_files); in tegra_dc_debugfs_init()
1611 dc->debugfs_files = NULL; in tegra_dc_debugfs_init()
1613 debugfs_remove(dc->debugfs); in tegra_dc_debugfs_init()
1614 dc->debugfs = NULL; in tegra_dc_debugfs_init()
1619 static int tegra_dc_debugfs_exit(struct tegra_dc *dc) in tegra_dc_debugfs_exit() argument
1621 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), in tegra_dc_debugfs_exit()
1622 dc->minor); in tegra_dc_debugfs_exit()
1623 dc->minor = NULL; in tegra_dc_debugfs_exit()
1625 kfree(dc->debugfs_files); in tegra_dc_debugfs_exit()
1626 dc->debugfs_files = NULL; in tegra_dc_debugfs_exit()
1628 debugfs_remove(dc->debugfs); in tegra_dc_debugfs_exit()
1629 dc->debugfs = NULL; in tegra_dc_debugfs_exit()
1637 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
1645 err = iommu_attach_device(tegra->domain, dc->dev); in tegra_dc_init()
1647 dev_err(dc->dev, "failed to attach to domain: %d\n", in tegra_dc_init()
1652 dc->domain = tegra->domain; in tegra_dc_init()
1655 primary = tegra_dc_primary_plane_create(drm, dc); in tegra_dc_init()
1661 if (dc->soc->supports_cursor) { in tegra_dc_init()
1662 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
1669 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
1674 drm_mode_crtc_set_gamma_size(&dc->base, 256); in tegra_dc_init()
1675 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
1681 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
1682 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
1684 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
1686 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
1690 err = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
1695 err = tegra_dc_debugfs_init(dc, drm->primary); in tegra_dc_init()
1697 dev_err(dc->dev, "debugfs setup failed: %d\n", err); in tegra_dc_init()
1700 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
1701 dev_name(dc->dev), dc); in tegra_dc_init()
1703 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
1709 if (dc->syncpt) { in tegra_dc_init()
1710 u32 syncpt = host1x_syncpt_id(dc->syncpt); in tegra_dc_init()
1713 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_dc_init()
1716 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_dc_init()
1720 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_dc_init()
1724 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_dc_init()
1729 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_dc_init()
1733 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_dc_init()
1736 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_dc_init()
1739 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_init()
1741 if (dc->soc->supports_border_color) in tegra_dc_init()
1742 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_dc_init()
1754 iommu_detach_device(tegra->domain, dc->dev); in tegra_dc_init()
1755 dc->domain = NULL; in tegra_dc_init()
1763 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
1766 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
1769 err = tegra_dc_debugfs_exit(dc); in tegra_dc_exit()
1771 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); in tegra_dc_exit()
1774 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
1776 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
1780 if (dc->domain) { in tegra_dc_exit()
1781 iommu_detach_device(dc->domain, dc->dev); in tegra_dc_exit()
1782 dc->domain = NULL; in tegra_dc_exit()
1848 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
1854 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
1856 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
1871 if (np == dc->dev->of_node) in tegra_dc_parse_dt()
1878 dc->pipe = value; in tegra_dc_parse_dt()
1888 struct tegra_dc *dc; in tegra_dc_probe() local
1891 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
1892 if (!dc) in tegra_dc_probe()
1899 spin_lock_init(&dc->lock); in tegra_dc_probe()
1900 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
1901 dc->dev = &pdev->dev; in tegra_dc_probe()
1902 dc->soc = id->data; in tegra_dc_probe()
1904 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
1908 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
1909 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
1911 return PTR_ERR(dc->clk); in tegra_dc_probe()
1914 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
1915 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
1917 return PTR_ERR(dc->rst); in tegra_dc_probe()
1920 if (dc->soc->has_powergate) { in tegra_dc_probe()
1921 if (dc->pipe == 0) in tegra_dc_probe()
1922 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
1924 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
1926 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_probe()
1927 dc->rst); in tegra_dc_probe()
1934 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
1941 err = reset_control_deassert(dc->rst); in tegra_dc_probe()
1950 dc->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dc_probe()
1951 if (IS_ERR(dc->regs)) in tegra_dc_probe()
1952 return PTR_ERR(dc->regs); in tegra_dc_probe()
1954 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
1955 if (dc->irq < 0) { in tegra_dc_probe()
1960 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
1961 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
1962 dc->client.dev = &pdev->dev; in tegra_dc_probe()
1964 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
1970 err = host1x_client_register(&dc->client); in tegra_dc_probe()
1977 dc->syncpt = host1x_syncpt_request(&pdev->dev, flags); in tegra_dc_probe()
1978 if (!dc->syncpt) in tegra_dc_probe()
1981 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
1988 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
1991 host1x_syncpt_free(dc->syncpt); in tegra_dc_remove()
1993 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
2000 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()
2006 reset_control_assert(dc->rst); in tegra_dc_remove()
2008 if (dc->soc->has_powergate) in tegra_dc_remove()
2009 tegra_powergate_power_off(dc->powergate); in tegra_dc_remove()
2011 clk_disable_unprepare(dc->clk); in tegra_dc_remove()