87 	u32 value;  in tegra_dc_readl_active()  local
92 	value = tegra_dc_readl(dc, offset);  in tegra_dc_readl_active()
96 	return value;  in tegra_dc_readl_active()
236 	unsigned long value, flags;  in tegra_dc_setup_window()  local
251 	value = WINDOW_A_SELECT << index;  in tegra_dc_setup_window()
252 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);  in tegra_dc_setup_window()
257 	value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);  in tegra_dc_setup_window()
258 	tegra_dc_writel(dc, value, DC_WIN_POSITION);  in tegra_dc_setup_window()
260 	value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);  in tegra_dc_setup_window()
261 	tegra_dc_writel(dc, value, DC_WIN_SIZE);  in tegra_dc_setup_window()
268 	value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);  in tegra_dc_setup_window()
269 	tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);  in tegra_dc_setup_window()
281 	value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);  in tegra_dc_setup_window()
282 	tegra_dc_writel(dc, value, DC_WIN_DDA_INC);  in tegra_dc_setup_window()
298 		value = window->stride[1] << 16 | window->stride[0];  in tegra_dc_setup_window()
299 		tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);  in tegra_dc_setup_window()
311 		unsigned long height = window->tiling.value;  in tegra_dc_setup_window()
315 			value = DC_WINBUF_SURFACE_KIND_PITCH;  in tegra_dc_setup_window()
319 			value = DC_WINBUF_SURFACE_KIND_TILED;  in tegra_dc_setup_window()
323 			value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |  in tegra_dc_setup_window()
328 		tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);  in tegra_dc_setup_window()
332 			value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |  in tegra_dc_setup_window()
337 			value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |  in tegra_dc_setup_window()
349 		tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);  in tegra_dc_setup_window()
352 	value = WIN_ENABLE;  in tegra_dc_setup_window()
365 		value |= CSC_ENABLE;  in tegra_dc_setup_window()
367 		value |= COLOR_EXPAND;  in tegra_dc_setup_window()
371 		value |= V_DIRECTION;  in tegra_dc_setup_window()
373 	tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);  in tegra_dc_setup_window()
599 	u32 value;  in tegra_plane_atomic_disable()  local
609 	value = WINDOW_A_SELECT << p->index;  in tegra_plane_atomic_disable()
610 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);  in tegra_plane_atomic_disable()
612 	value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);  in tegra_plane_atomic_disable()
613 	value &= ~WIN_ENABLE;  in tegra_plane_atomic_disable()
614 	tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);  in tegra_plane_atomic_disable()
708 	u32 value = CURSOR_CLIP_DISPLAY;  in tegra_cursor_atomic_update()  local
716 		value |= CURSOR_SIZE_32x32;  in tegra_cursor_atomic_update()
720 		value |= CURSOR_SIZE_64x64;  in tegra_cursor_atomic_update()
724 		value |= CURSOR_SIZE_128x128;  in tegra_cursor_atomic_update()
728 		value |= CURSOR_SIZE_256x256;  in tegra_cursor_atomic_update()
737 	value |= (bo->paddr >> 10) & 0x3fffff;  in tegra_cursor_atomic_update()
738 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);  in tegra_cursor_atomic_update()
741 	value = (bo->paddr >> 32) & 0x3;  in tegra_cursor_atomic_update()
742 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);  in tegra_cursor_atomic_update()
746 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_update()
747 	value |= CURSOR_ENABLE;  in tegra_cursor_atomic_update()
748 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_update()
750 	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);  in tegra_cursor_atomic_update()
751 	value &= ~CURSOR_DST_BLEND_MASK;  in tegra_cursor_atomic_update()
752 	value &= ~CURSOR_SRC_BLEND_MASK;  in tegra_cursor_atomic_update()
753 	value |= CURSOR_MODE_NORMAL;  in tegra_cursor_atomic_update()
754 	value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;  in tegra_cursor_atomic_update()
755 	value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;  in tegra_cursor_atomic_update()
756 	value |= CURSOR_ALPHA;  in tegra_cursor_atomic_update()
757 	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);  in tegra_cursor_atomic_update()
760 	value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);  in tegra_cursor_atomic_update()
761 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);  in tegra_cursor_atomic_update()
769 	u32 value;  in tegra_cursor_atomic_disable()  local
777 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
778 	value &= ~CURSOR_ENABLE;  in tegra_cursor_atomic_disable()
779 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
922 	unsigned long value, flags;  in tegra_dc_enable_vblank()  local
926 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
927 	value |= VBLANK_INT;  in tegra_dc_enable_vblank()
928 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
935 	unsigned long value, flags;  in tegra_dc_disable_vblank()  local
939 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
940 	value &= ~VBLANK_INT;  in tegra_dc_disable_vblank()
941 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
1057 	u32 value;  in tegra_dc_stop()  local
1060 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
1061 	value &= ~DISP_CTRL_MODE_MASK;  in tegra_dc_stop()
1062 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
1069 	u32 value;  in tegra_dc_idle()  local
1071 	value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_idle()
1073 	return (value & DISP_CTRL_MODE_MASK) == 0;  in tegra_dc_idle()
1094 	u32 value;  in tegra_crtc_disable()  local
1123 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_disable()
1124 		value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |  in tegra_crtc_disable()
1126 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_disable()
1144 	unsigned long value;  in tegra_dc_set_timings()  local
1148 	value = (v_ref_to_sync << 16) | h_ref_to_sync;  in tegra_dc_set_timings()
1149 	tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);  in tegra_dc_set_timings()
1151 	value = ((mode->vsync_end - mode->vsync_start) << 16) |  in tegra_dc_set_timings()
1153 	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);  in tegra_dc_set_timings()
1155 	value = ((mode->vtotal - mode->vsync_end) << 16) |  in tegra_dc_set_timings()
1157 	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);  in tegra_dc_set_timings()
1159 	value = ((mode->vsync_start - mode->vdisplay) << 16) |  in tegra_dc_set_timings()
1161 	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);  in tegra_dc_set_timings()
1163 	value = (mode->vdisplay << 16) | mode->hdisplay;  in tegra_dc_set_timings()
1164 	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);  in tegra_dc_set_timings()
1201 	u32 value;  in tegra_dc_commit_state()  local
1228 	value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;  in tegra_dc_commit_state()
1229 	tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);  in tegra_dc_commit_state()
1237 	u32 value;  in tegra_crtc_mode_set_nofb()  local
1246 		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_mode_set_nofb()
1247 		value &= ~INTERLACE_ENABLE;  in tegra_crtc_mode_set_nofb()
1248 		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_mode_set_nofb()
1251 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_mode_set_nofb()
1252 	value &= ~DISP_CTRL_MODE_MASK;  in tegra_crtc_mode_set_nofb()
1253 	value |= DISP_CTRL_MODE_C_DISPLAY;  in tegra_crtc_mode_set_nofb()
1254 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_mode_set_nofb()
1256 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_mode_set_nofb()
1257 	value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |  in tegra_crtc_mode_set_nofb()
1259 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_mode_set_nofb()
1641 	u32 value;  in tegra_dc_init()  local
1712 		value = SYNCPT_CNTRL_NO_STALL;  in tegra_dc_init()
1713 		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);  in tegra_dc_init()
1715 		value = SYNCPT_VSYNC_ENABLE | syncpt;  in tegra_dc_init()
1716 		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);  in tegra_dc_init()
1719 	value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;  in tegra_dc_init()
1720 	tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_dc_init()
1722 	value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |  in tegra_dc_init()
1724 	tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_dc_init()
1727 	value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |  in tegra_dc_init()
1729 	tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);  in tegra_dc_init()
1731 	value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |  in tegra_dc_init()
1733 	tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);  in tegra_dc_init()
1735 	value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;  in tegra_dc_init()
1736 	tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_dc_init()
1738 	value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;  in tegra_dc_init()
1739 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_init()
1851 	u32 value = 0;  in tegra_dc_parse_dt()  local
1854 	err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);  in tegra_dc_parse_dt()
1874 			value++;  in tegra_dc_parse_dt()
1878 	dc->pipe = value;  in tegra_dc_parse_dt()