66 				      unsigned long value,  in tegra_dpaux_writel()  argument
69 	writel(value, dpaux->regs + (offset << 2));  in tegra_dpaux_writel()
79 		unsigned long value = 0;  in tegra_dpaux_write_fifo()  local
82 			value |= buffer[i * 4 + j] << (j * 8);  in tegra_dpaux_write_fifo()
84 		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));  in tegra_dpaux_write_fifo()
95 		unsigned long value;  in tegra_dpaux_read_fifo()  local
97 		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));  in tegra_dpaux_read_fifo()
100 			buffer[i * 4 + j] = value >> (j * 8);  in tegra_dpaux_read_fifo()
111 	u32 value;  in tegra_dpaux_transfer()  local
125 			value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;  in tegra_dpaux_transfer()
133 		value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);  in tegra_dpaux_transfer()
139 			value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;  in tegra_dpaux_transfer()
141 			value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;  in tegra_dpaux_transfer()
147 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;  in tegra_dpaux_transfer()
149 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;  in tegra_dpaux_transfer()
155 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;  in tegra_dpaux_transfer()
157 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;  in tegra_dpaux_transfer()
162 		value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;  in tegra_dpaux_transfer()
166 		value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;  in tegra_dpaux_transfer()
174 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
182 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
183 	value |= DPAUX_DP_AUXCTL_TRANSACTREQ;  in tegra_dpaux_transfer()
184 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
191 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_transfer()
194 	if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)  in tegra_dpaux_transfer()
197 	if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||  in tegra_dpaux_transfer()
198 	    (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||  in tegra_dpaux_transfer()
199 	    (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))  in tegra_dpaux_transfer()
202 	switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {  in tegra_dpaux_transfer()
226 			size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;  in tegra_dpaux_transfer()
251 	unsigned long value;  in tegra_dpaux_irq()  local
254 	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
255 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
257 	if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))  in tegra_dpaux_irq()
260 	if (value & DPAUX_INTR_IRQ_EVENT) {  in tegra_dpaux_irq()
264 	if (value & DPAUX_INTR_AUX_DONE)  in tegra_dpaux_irq()
274 	unsigned long value;  in tegra_dpaux_probe()  local
346 	value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |  in tegra_dpaux_probe()
348 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);  in tegra_dpaux_probe()
349 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_probe()
466 	unsigned long value;  in tegra_dpaux_detect()  local
468 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_detect()
470 	if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)  in tegra_dpaux_detect()
478 	unsigned long value;  in tegra_dpaux_enable()  local
480 	value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |  in tegra_dpaux_enable()
485 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_enable()
487 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_enable()
488 	value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_enable()
489 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_enable()
496 	unsigned long value;  in tegra_dpaux_disable()  local
498 	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_disable()
499 	value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_disable()
500 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_disable()