112 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,  in tegra_dsi_writel()  argument
115 	writel(value, dsi->regs + (reg << 2));  in tegra_dsi_writel()
369 	u32 value;  in tegra_dsi_set_phy_timing()  local
371 	value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |  in tegra_dsi_set_phy_timing()
375 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);  in tegra_dsi_set_phy_timing()
377 	value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |  in tegra_dsi_set_phy_timing()
381 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);  in tegra_dsi_set_phy_timing()
383 	value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |  in tegra_dsi_set_phy_timing()
386 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);  in tegra_dsi_set_phy_timing()
388 	value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |  in tegra_dsi_set_phy_timing()
391 	tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);  in tegra_dsi_set_phy_timing()
454 	u32 value;  in tegra_dsi_ganged_enable()  local
459 	value = DSI_GANGED_MODE_CONTROL_ENABLE;  in tegra_dsi_ganged_enable()
460 	tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);  in tegra_dsi_ganged_enable()
465 	u32 value;  in tegra_dsi_enable()  local
467 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_enable()
468 	value |= DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_enable()
469 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_enable()
492 	u32 value;  in tegra_dsi_configure()  local
514 	value = DSI_CONTROL_CHANNEL(0) |  in tegra_dsi_configure()
518 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
522 	value = DSI_HOST_CONTROL_HS;  in tegra_dsi_configure()
523 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_configure()
525 	value = tegra_dsi_readl(dsi, DSI_CONTROL);  in tegra_dsi_configure()
528 		value |= DSI_CONTROL_HS_CLK_CTRL;  in tegra_dsi_configure()
530 	value &= ~DSI_CONTROL_TX_TRIG(3);  in tegra_dsi_configure()
534 		value &= ~DSI_CONTROL_DCS_ENABLE;  in tegra_dsi_configure()
536 		value |= DSI_CONTROL_DCS_ENABLE;  in tegra_dsi_configure()
538 	value |= DSI_CONTROL_VIDEO_ENABLE;  in tegra_dsi_configure()
539 	value &= ~DSI_CONTROL_HOST_ENABLE;  in tegra_dsi_configure()
540 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
588 		value = MIPI_DCS_WRITE_MEMORY_START << 8 |  in tegra_dsi_configure()
590 		tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);  in tegra_dsi_configure()
605 			value = bclk - bclk_ganged + delay + 20;  in tegra_dsi_configure()
608 			value = 8 * mul / div;  in tegra_dsi_configure()
611 		tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);  in tegra_dsi_configure()
629 	u32 value;  in tegra_dsi_wait_idle()  local
634 		value = tegra_dsi_readl(dsi, DSI_STATUS);  in tegra_dsi_wait_idle()
635 		if (value & DSI_STATUS_IDLE)  in tegra_dsi_wait_idle()
646 	u32 value;  in tegra_dsi_video_disable()  local
648 	value = tegra_dsi_readl(dsi, DSI_CONTROL);  in tegra_dsi_video_disable()
649 	value &= ~DSI_CONTROL_VIDEO_ENABLE;  in tegra_dsi_video_disable()
650 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_video_disable()
667 	u32 value;  in tegra_dsi_set_timeout()  local
671 	value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);  in tegra_dsi_set_timeout()
672 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);  in tegra_dsi_set_timeout()
676 	value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);  in tegra_dsi_set_timeout()
677 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);  in tegra_dsi_set_timeout()
679 	value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);  in tegra_dsi_set_timeout()
680 	tegra_dsi_writel(dsi, value, DSI_TO_TALLY);  in tegra_dsi_set_timeout()
688 	u32 value;  in tegra_dsi_disable()  local
695 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_disable()
696 	value &= ~DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_disable()
697 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_disable()
707 	u32 value;  in tegra_dsi_soft_reset()  local
709 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
710 	value &= ~DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_soft_reset()
711 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
715 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
716 	value |= DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_soft_reset()
717 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
721 	value = tegra_dsi_readl(dsi, DSI_TRIGGER);  in tegra_dsi_soft_reset()
722 	if (value)  in tegra_dsi_soft_reset()
805 	u32 value;  in tegra_dsi_encoder_mode_set()  local
823 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_mode_set()
824 	value |= DSI_ENABLE;  in tegra_dsi_encoder_mode_set()
825 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_mode_set()
843 	u32 value;  in tegra_dsi_encoder_disable()  local
856 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_disable()
857 		value &= ~DSI_ENABLE;  in tegra_dsi_encoder_disable()
858 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_dsi_encoder_disable()
969 	u32 value;  in tegra_dsi_pad_enable()  local
971 	value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);  in tegra_dsi_pad_enable()
972 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);  in tegra_dsi_pad_enable()
979 	u32 value;  in tegra_dsi_pad_calibrate()  local
990 	value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |  in tegra_dsi_pad_calibrate()
993 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);  in tegra_dsi_pad_calibrate()
1119 	u32 value;  in tegra_dsi_read_response()  local
1122 	value = tegra_dsi_readl(dsi, DSI_RD_DATA);  in tegra_dsi_read_response()
1124 	switch (value & 0x3f) {  in tegra_dsi_read_response()
1126 		errors = (value >> 8) & 0xffff;  in tegra_dsi_read_response()
1136 		rx[0] = (value >> 8) & 0xff;  in tegra_dsi_read_response()
1141 		rx[0] = (value >>  8) & 0xff;  in tegra_dsi_read_response()
1142 		rx[1] = (value >> 16) & 0xff;  in tegra_dsi_read_response()
1147 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);  in tegra_dsi_read_response()
1151 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);  in tegra_dsi_read_response()
1156 			value & 0x3f);  in tegra_dsi_read_response()
1166 			value = tegra_dsi_readl(dsi, DSI_RD_DATA);  in tegra_dsi_read_response()
1169 				rx[j + k] = (value >> (k << 3)) & 0xff;  in tegra_dsi_read_response()
1183 		u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);  in tegra_dsi_transmit()  local
1184 		if ((value & DSI_TRIGGER_HOST) == 0)  in tegra_dsi_transmit()
1200 		u32 value = tegra_dsi_readl(dsi, DSI_STATUS);  in tegra_dsi_wait_for_response()  local
1201 		u8 count = value & 0x1f;  in tegra_dsi_wait_for_response()
1218 	u32 value;  in tegra_dsi_writesl()  local
1221 		value = 0;  in tegra_dsi_writesl()
1224 			value |= buf[j + i] << (i << 3);  in tegra_dsi_writesl()
1226 		tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_writesl()
1238 	u32 value;  in tegra_dsi_host_transfer()  local
1251 	value = tegra_dsi_readl(dsi, DSI_STATUS);  in tegra_dsi_host_transfer()
1252 	if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {  in tegra_dsi_host_transfer()
1253 		value = DSI_HOST_CONTROL_FIFO_RESET;  in tegra_dsi_host_transfer()
1254 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1258 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);  in tegra_dsi_host_transfer()
1259 	value |= DSI_POWER_CONTROL_ENABLE;  in tegra_dsi_host_transfer()
1260 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_host_transfer()
1264 	value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |  in tegra_dsi_host_transfer()
1268 		value |= DSI_HOST_CONTROL_HS;  in tegra_dsi_host_transfer()
1275 		value |= DSI_HOST_CONTROL_FIFO_SEL;  in tegra_dsi_host_transfer()
1277 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1285 		value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1286 		value |= DSI_HOST_CONTROL_PKT_BTA;  in tegra_dsi_host_transfer()
1287 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1290 	value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;  in tegra_dsi_host_transfer()
1291 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_host_transfer()
1294 	value = header[2] << 16 | header[1] << 8 | header[0];  in tegra_dsi_host_transfer()
1295 	tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_host_transfer()
1314 		value = tegra_dsi_readl(dsi, DSI_RD_DATA);  in tegra_dsi_host_transfer()
1315 		switch (value) {  in tegra_dsi_host_transfer()
1329 			dev_err(dsi->dev, "unknown status: %08x\n", value);  in tegra_dsi_host_transfer()