Lines Matching refs:pll1
28 u32 pll1; member
173 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
206 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
220 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
234 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
251 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
269 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
288 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
307 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
330 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
348 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
367 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
386 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
748 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); in tegra_hdmi_setup_tmds()