Lines Matching refs:value
78 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
81 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
89 u32 value; in tegra_sor_dp_train_fast() local
93 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | in tegra_sor_dp_train_fast()
97 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); in tegra_sor_dp_train_fast()
99 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | in tegra_sor_dp_train_fast()
103 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); in tegra_sor_dp_train_fast()
105 value = SOR_LANE_POST_CURSOR_LANE3(0x00) | in tegra_sor_dp_train_fast()
109 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); in tegra_sor_dp_train_fast()
114 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); in tegra_sor_dp_train_fast()
115 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_train_fast()
116 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_train_fast()
117 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ in tegra_sor_dp_train_fast()
118 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); in tegra_sor_dp_train_fast()
120 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); in tegra_sor_dp_train_fast()
121 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
123 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); in tegra_sor_dp_train_fast()
127 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); in tegra_sor_dp_train_fast()
128 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
130 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); in tegra_sor_dp_train_fast()
136 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
140 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
143 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
151 value = tegra_sor_readl(sor, SOR_DP_SPARE_0); in tegra_sor_dp_train_fast()
152 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_train_fast()
153 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_train_fast()
154 value |= SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_dp_train_fast()
155 tegra_sor_writel(sor, value, SOR_DP_SPARE_0); in tegra_sor_dp_train_fast()
157 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
161 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
164 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
172 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
176 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
179 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
206 u32 value; in tegra_sor_setup_pwm() local
208 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
209 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
210 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
211 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
213 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
214 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
215 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
216 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
217 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
218 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
223 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
224 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
235 unsigned long value, timeout; in tegra_sor_attach() local
238 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); in tegra_sor_attach()
239 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
240 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
241 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); in tegra_sor_attach()
245 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); in tegra_sor_attach()
246 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
247 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); in tegra_sor_attach()
253 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
254 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
265 unsigned long value, timeout; in tegra_sor_wakeup() local
271 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
272 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
274 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
285 u32 value; in tegra_sor_power_up() local
287 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
288 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
289 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
294 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
295 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
481 unsigned long value, timeout; in tegra_sor_detach() local
484 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); in tegra_sor_detach()
485 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
486 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); in tegra_sor_detach()
492 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
493 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
497 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
501 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); in tegra_sor_detach()
502 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
503 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); in tegra_sor_detach()
507 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); in tegra_sor_detach()
508 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
509 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); in tegra_sor_detach()
515 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
516 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
522 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
530 unsigned long value, timeout; in tegra_sor_power_down() local
533 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
534 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
535 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
536 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
541 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
542 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
548 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
555 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); in tegra_sor_power_down()
556 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down()
558 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); in tegra_sor_power_down()
561 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down()
563 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
568 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
569 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down()
575 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down()
578 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_power_down()
579 value |= SOR_PLL_2_PORT_POWERDOWN; in tegra_sor_power_down()
580 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_power_down()
584 value = tegra_sor_readl(sor, SOR_PLL_0); in tegra_sor_power_down()
585 value |= SOR_PLL_0_POWER_OFF; in tegra_sor_power_down()
586 value |= SOR_PLL_0_VCOPD; in tegra_sor_power_down()
587 tegra_sor_writel(sor, value, SOR_PLL_0); in tegra_sor_power_down()
589 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_power_down()
590 value |= SOR_PLL_2_SEQ_PLLCAPPD; in tegra_sor_power_down()
591 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
592 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_power_down()
613 u32 value; in tegra_sor_crc_wait() local
618 value = tegra_sor_readl(sor, SOR_CRC_A); in tegra_sor_crc_wait()
619 if (value & SOR_CRC_A_VALID) in tegra_sor_crc_wait()
634 u32 value; in tegra_sor_crc_read() local
643 value = tegra_sor_readl(sor, SOR_STATE_1); in tegra_sor_crc_read()
644 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_crc_read()
645 tegra_sor_writel(sor, value, SOR_STATE_1); in tegra_sor_crc_read()
647 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_crc_read()
648 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_crc_read()
649 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_crc_read()
651 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_crc_read()
652 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_crc_read()
653 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_crc_read()
660 value = tegra_sor_readl(sor, SOR_CRC_B); in tegra_sor_crc_read()
662 num = scnprintf(buf, sizeof(buf), "%08x\n", value); in tegra_sor_crc_read()
953 u32 value; in tegra_sor_encoder_mode_set() local
997 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
998 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_encoder_mode_set()
999 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_encoder_mode_set()
1000 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
1002 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1003 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; in tegra_sor_encoder_mode_set()
1004 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1007 value = tegra_sor_readl(sor, SOR_PLL_3); in tegra_sor_encoder_mode_set()
1008 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; in tegra_sor_encoder_mode_set()
1009 tegra_sor_writel(sor, value, SOR_PLL_3); in tegra_sor_encoder_mode_set()
1011 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | in tegra_sor_encoder_mode_set()
1013 tegra_sor_writel(sor, value, SOR_PLL_0); in tegra_sor_encoder_mode_set()
1015 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1016 value |= SOR_PLL_2_SEQ_PLLCAPPD; in tegra_sor_encoder_mode_set()
1017 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_encoder_mode_set()
1018 value |= SOR_PLL_2_LVDS_ENABLE; in tegra_sor_encoder_mode_set()
1019 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1021 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; in tegra_sor_encoder_mode_set()
1022 tegra_sor_writel(sor, value, SOR_PLL_1); in tegra_sor_encoder_mode_set()
1025 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1026 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) in tegra_sor_encoder_mode_set()
1032 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1033 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; in tegra_sor_encoder_mode_set()
1034 value &= ~SOR_PLL_2_PORT_POWERDOWN; in tegra_sor_encoder_mode_set()
1035 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1042 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
1043 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_encoder_mode_set()
1044 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; in tegra_sor_encoder_mode_set()
1045 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
1048 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1049 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | in tegra_sor_encoder_mode_set()
1051 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1053 value = tegra_sor_readl(sor, SOR_PLL_0); in tegra_sor_encoder_mode_set()
1054 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; in tegra_sor_encoder_mode_set()
1055 tegra_sor_writel(sor, value, SOR_PLL_0); in tegra_sor_encoder_mode_set()
1057 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); in tegra_sor_encoder_mode_set()
1058 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_encoder_mode_set()
1059 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); in tegra_sor_encoder_mode_set()
1071 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1072 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; in tegra_sor_encoder_mode_set()
1073 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1078 value = tegra_sor_readl(sor, SOR_PLL_0); in tegra_sor_encoder_mode_set()
1079 value &= ~SOR_PLL_0_POWER_OFF; in tegra_sor_encoder_mode_set()
1080 value &= ~SOR_PLL_0_VCOPD; in tegra_sor_encoder_mode_set()
1081 tegra_sor_writel(sor, value, SOR_PLL_0); in tegra_sor_encoder_mode_set()
1083 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1084 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_encoder_mode_set()
1085 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1090 value = tegra_sor_readl(sor, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1091 value &= ~SOR_PLL_2_PORT_POWERDOWN; in tegra_sor_encoder_mode_set()
1092 tegra_sor_writel(sor, value, SOR_PLL_2); in tegra_sor_encoder_mode_set()
1100 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); in tegra_sor_encoder_mode_set()
1103 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); in tegra_sor_encoder_mode_set()
1105 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; in tegra_sor_encoder_mode_set()
1108 value &= ~SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_encoder_mode_set()
1110 value |= SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_encoder_mode_set()
1113 value &= ~SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_encoder_mode_set()
1115 value |= SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_encoder_mode_set()
1117 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); in tegra_sor_encoder_mode_set()
1119 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); in tegra_sor_encoder_mode_set()
1120 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_encoder_mode_set()
1121 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); in tegra_sor_encoder_mode_set()
1122 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); in tegra_sor_encoder_mode_set()
1125 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_encoder_mode_set()
1127 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_encoder_mode_set()
1130 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_encoder_mode_set()
1131 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_encoder_mode_set()
1138 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
1139 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_encoder_mode_set()
1140 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; in tegra_sor_encoder_mode_set()
1141 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
1144 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); in tegra_sor_encoder_mode_set()
1145 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_encoder_mode_set()
1147 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_encoder_mode_set()
1148 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); in tegra_sor_encoder_mode_set()
1150 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_encoder_mode_set()
1151 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); in tegra_sor_encoder_mode_set()
1153 for (i = 0, value = 0; i < 4; i++) { in tegra_sor_encoder_mode_set()
1157 value = (value << 8) | lane; in tegra_sor_encoder_mode_set()
1160 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_encoder_mode_set()
1162 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); in tegra_sor_encoder_mode_set()
1163 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_encoder_mode_set()
1164 value |= SOR_DP_CONFIG_WATERMARK(config.watermark); in tegra_sor_encoder_mode_set()
1166 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_encoder_mode_set()
1167 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); in tegra_sor_encoder_mode_set()
1169 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_encoder_mode_set()
1170 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); in tegra_sor_encoder_mode_set()
1173 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_encoder_mode_set()
1175 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_encoder_mode_set()
1177 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_encoder_mode_set()
1178 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_encoder_mode_set()
1179 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); in tegra_sor_encoder_mode_set()
1181 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_encoder_mode_set()
1182 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_encoder_mode_set()
1183 value |= config.hblank_symbols & 0xffff; in tegra_sor_encoder_mode_set()
1184 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_encoder_mode_set()
1186 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_encoder_mode_set()
1187 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_encoder_mode_set()
1188 value |= config.vblank_symbols & 0xffff; in tegra_sor_encoder_mode_set()
1189 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_encoder_mode_set()
1192 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); in tegra_sor_encoder_mode_set()
1193 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_encoder_mode_set()
1194 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); in tegra_sor_encoder_mode_set()
1223 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
1224 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_encoder_mode_set()
1225 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_encoder_mode_set()
1226 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_encoder_mode_set()
1228 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); in tegra_sor_encoder_mode_set()
1229 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_encoder_mode_set()
1230 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_encoder_mode_set()
1233 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_encoder_mode_set()
1235 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); in tegra_sor_encoder_mode_set()
1243 value = (value << 8) | lane; in tegra_sor_encoder_mode_set()
1246 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_encoder_mode_set()
1268 value = SOR_STATE_ASY_PROTOCOL_DP_A | in tegra_sor_encoder_mode_set()
1273 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_encoder_mode_set()
1276 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_encoder_mode_set()
1279 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_encoder_mode_set()
1282 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_encoder_mode_set()
1286 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_encoder_mode_set()
1290 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_encoder_mode_set()
1298 tegra_sor_writel(sor, value, SOR_STATE_1); in tegra_sor_encoder_mode_set()
1305 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_encoder_mode_set()
1306 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); in tegra_sor_encoder_mode_set()
1311 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_encoder_mode_set()
1312 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); in tegra_sor_encoder_mode_set()
1317 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_encoder_mode_set()
1318 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); in tegra_sor_encoder_mode_set()
1323 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_encoder_mode_set()
1324 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); in tegra_sor_encoder_mode_set()
1327 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_encoder_mode_set()
1329 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_encoder_mode_set()
1340 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_encoder_mode_set()
1341 value |= SOR_ENABLE; in tegra_sor_encoder_mode_set()
1342 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_encoder_mode_set()
1372 u32 value; in tegra_sor_encoder_disable() local
1397 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_encoder_disable()
1398 value &= ~SOR_ENABLE; in tegra_sor_encoder_disable()
1399 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_encoder_disable()