36 #define PCH_I2CCTL	0x04	/* I2C control register */  macro
230 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);  in pch_i2c_init()
252 	iowrite32(reg_value, p + PCH_I2CCTL);  in pch_i2c_init()
256 		ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);  in pch_i2c_init()
305 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_start()
306 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);  in pch_i2c_start()
316 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_stop()
318 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);  in pch_i2c_stop()
362 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_repstart()
363 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);  in pch_i2c_repstart()
393 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);  in pch_i2c_writebytes()
395 	pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),  in pch_i2c_writebytes()
457 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_sendack()
458 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);  in pch_i2c_sendack()
468 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_sendnack()
469 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);  in pch_i2c_sendnack()
481 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));  in pch_i2c_restart()
482 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);  in pch_i2c_restart()
511 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);  in pch_i2c_readbytes()
731 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);  in pch_i2c_disbl_int()