Lines Matching refs:SW_TWSI_EOP_TWSI_CTL
39 #define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull macro
192 return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0; in octeon_i2c_test_iflg()
235 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, in octeon_i2c_start()
247 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, in octeon_i2c_start()
275 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, in octeon_i2c_stop()
309 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); in octeon_i2c_write()
325 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); in octeon_i2c_write()
360 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); in octeon_i2c_read()
376 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, in octeon_i2c_read()
379 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, in octeon_i2c_read()
496 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); in octeon_i2c_initlowlevel()