Lines Matching refs:qib_read_kreg32
351 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, in qib_read_kreg32() function
717 qib_read_kreg32(dd, kr_scratch); in qib_6120_clear_freeze()
793 ctrl = qib_read_kreg32(dd, kr_control); in qib_handle_6120_hwerrors()
1563 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); in unlikely_6120_intr()
1588 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); in unlikely_6120_intr()
1625 istat = qib_read_kreg32(dd, kr_intstatus); in qib_6120intr()
2075 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt); in qib_6120_config_ctxts()
2303 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_6120_mod()
2305 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_6120_mod()
2307 qib_read_kreg32(dd, kr_scratch); in sendctrl_6120_mod()
2636 ctrl = qib_read_kreg32(dd, kr_control); in qib_chk_6120_errormask()
2717 qib_read_kreg32(dd, kr_scratch); in qib_6120_xgxs_reset()
3122 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); in get_6120_chip_params()
3124 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); in get_6120_chip_params()
3125 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); in get_6120_chip_params()
3126 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); in get_6120_chip_params()
3127 dd->palign = qib_read_kreg32(dd, kr_palign); in get_6120_chip_params()
3131 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in get_6120_chip_params()
3176 cregbase = qib_read_kreg32(dd, kr_counterregbase); in set_6120_baseaddrs()
3312 dd->ureg_align = qib_read_kreg32(dd, kr_palign); in init_6120_variables()