534 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);  in __arm_smmu_tlb_sync()
563 		writel_relaxed(ARM_SMMU_CB_ASID(cfg),  in arm_smmu_tlb_inv_context()
567 		writel_relaxed(ARM_SMMU_CB_VMID(cfg),  in arm_smmu_tlb_inv_context()
590 			writel_relaxed(iova, reg);  in arm_smmu_tlb_inv_range_nosync()
607 		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);  in arm_smmu_tlb_inv_range_nosync()
689 		writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);  in arm_smmu_context_fault()
743 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));  in arm_smmu_init_context_bank()
761 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));  in arm_smmu_init_context_bank()
766 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);  in arm_smmu_init_context_bank()
769 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);  in arm_smmu_init_context_bank()
772 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);  in arm_smmu_init_context_bank()
775 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);  in arm_smmu_init_context_bank()
778 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);  in arm_smmu_init_context_bank()
780 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);  in arm_smmu_init_context_bank()
786 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
790 			writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);  in arm_smmu_init_context_bank()
794 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
800 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);  in arm_smmu_init_context_bank()
802 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);  in arm_smmu_init_context_bank()
812 	writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_init_context_bank()
959 	writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_destroy_domain_context()
1045 		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));  in arm_smmu_master_configure_smrs()
1072 		writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));  in arm_smmu_master_free_smrs()
1098 		writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));  in arm_smmu_domain_add_master()
1122 		writel_relaxed(S2CR_TYPE_BYPASS,  in arm_smmu_domain_remove_master()
1237 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);  in arm_smmu_iova_to_phys_hard()
1240 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);  in arm_smmu_iova_to_phys_hard()
1242 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);  in arm_smmu_iova_to_phys_hard()
1474 		writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));  in arm_smmu_device_reset()
1475 		writel_relaxed(S2CR_TYPE_BYPASS,  in arm_smmu_device_reset()
1482 		writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_device_reset()
1483 		writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_device_reset()
1487 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);  in arm_smmu_device_reset()
1488 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);  in arm_smmu_device_reset()
1594 		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));  in arm_smmu_device_cfg_probe()