76 static void free_iommu(struct intel_iommu *iommu);
426 	if (dmaru->iommu)  in dmar_free_drhd()
427 		free_iommu(dmaru->iommu);  in dmar_free_drhd()
465 			drhd->iommu->node = node;  in dmar_parse_one_rhsa()
891 		x86_init.iommu.iommu_init = intel_iommu_init;  in detect_intel_iommu()
902 static void unmap_iommu(struct intel_iommu *iommu)  in unmap_iommu()  argument
904 	iounmap(iommu->reg);  in unmap_iommu()
905 	release_mem_region(iommu->reg_phys, iommu->reg_size);  in unmap_iommu()
916 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)  in map_iommu()  argument
920 	iommu->reg_phys = phys_addr;  in map_iommu()
921 	iommu->reg_size = VTD_PAGE_SIZE;  in map_iommu()
923 	if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {  in map_iommu()
929 	iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);  in map_iommu()
930 	if (!iommu->reg) {  in map_iommu()
936 	iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);  in map_iommu()
937 	iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);  in map_iommu()
939 	if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {  in map_iommu()
946 	map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),  in map_iommu()
947 			 cap_max_fault_reg_offset(iommu->cap));  in map_iommu()
949 	if (map_size > iommu->reg_size) {  in map_iommu()
950 		iounmap(iommu->reg);  in map_iommu()
951 		release_mem_region(iommu->reg_phys, iommu->reg_size);  in map_iommu()
952 		iommu->reg_size = map_size;  in map_iommu()
953 		if (!request_mem_region(iommu->reg_phys, iommu->reg_size,  in map_iommu()
954 					iommu->name)) {  in map_iommu()
959 		iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);  in map_iommu()
960 		if (!iommu->reg) {  in map_iommu()
970 	iounmap(iommu->reg);  in map_iommu()
972 	release_mem_region(iommu->reg_phys, iommu->reg_size);  in map_iommu()
977 static int dmar_alloc_seq_id(struct intel_iommu *iommu)  in dmar_alloc_seq_id()  argument
979 	iommu->seq_id = find_first_zero_bit(dmar_seq_ids,  in dmar_alloc_seq_id()
981 	if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {  in dmar_alloc_seq_id()
982 		iommu->seq_id = -1;  in dmar_alloc_seq_id()
984 		set_bit(iommu->seq_id, dmar_seq_ids);  in dmar_alloc_seq_id()
985 		sprintf(iommu->name, "dmar%d", iommu->seq_id);  in dmar_alloc_seq_id()
988 	return iommu->seq_id;  in dmar_alloc_seq_id()
991 static void dmar_free_seq_id(struct intel_iommu *iommu)  in dmar_free_seq_id()  argument
993 	if (iommu->seq_id >= 0) {  in dmar_free_seq_id()
994 		clear_bit(iommu->seq_id, dmar_seq_ids);  in dmar_free_seq_id()
995 		iommu->seq_id = -1;  in dmar_free_seq_id()
1001 	struct intel_iommu *iommu;  in alloc_iommu()  local
1012 	iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);  in alloc_iommu()
1013 	if (!iommu)  in alloc_iommu()
1016 	if (dmar_alloc_seq_id(iommu) < 0) {  in alloc_iommu()
1022 	err = map_iommu(iommu, drhd->reg_base_addr);  in alloc_iommu()
1024 		pr_err("IOMMU: failed to map %s\n", iommu->name);  in alloc_iommu()
1029 	agaw = iommu_calculate_agaw(iommu);  in alloc_iommu()
1032 			iommu->seq_id);  in alloc_iommu()
1035 	msagaw = iommu_calculate_max_sagaw(iommu);  in alloc_iommu()
1038 			iommu->seq_id);  in alloc_iommu()
1041 	iommu->agaw = agaw;  in alloc_iommu()
1042 	iommu->msagaw = msagaw;  in alloc_iommu()
1043 	iommu->segment = drhd->segment;  in alloc_iommu()
1045 	iommu->node = -1;  in alloc_iommu()
1047 	ver = readl(iommu->reg + DMAR_VER_REG);  in alloc_iommu()
1049 		iommu->seq_id,  in alloc_iommu()
1052 		(unsigned long long)iommu->cap,  in alloc_iommu()
1053 		(unsigned long long)iommu->ecap);  in alloc_iommu()
1056 	sts = readl(iommu->reg + DMAR_GSTS_REG);  in alloc_iommu()
1058 		iommu->gcmd |= DMA_GCMD_IRE;  in alloc_iommu()
1060 		iommu->gcmd |= DMA_GCMD_TE;  in alloc_iommu()
1062 		iommu->gcmd |= DMA_GCMD_QIE;  in alloc_iommu()
1064 	raw_spin_lock_init(&iommu->register_lock);  in alloc_iommu()
1066 	drhd->iommu = iommu;  in alloc_iommu()
1069 		iommu->iommu_dev = iommu_device_create(NULL, iommu,  in alloc_iommu()
1071 						       iommu->name);  in alloc_iommu()
1076 	unmap_iommu(iommu);  in alloc_iommu()
1078 	dmar_free_seq_id(iommu);  in alloc_iommu()
1080 	kfree(iommu);  in alloc_iommu()
1084 static void free_iommu(struct intel_iommu *iommu)  in free_iommu()  argument
1086 	iommu_device_destroy(iommu->iommu_dev);  in free_iommu()
1088 	if (iommu->irq) {  in free_iommu()
1089 		free_irq(iommu->irq, iommu);  in free_iommu()
1090 		irq_set_handler_data(iommu->irq, NULL);  in free_iommu()
1091 		dmar_free_hwirq(iommu->irq);  in free_iommu()
1094 	if (iommu->qi) {  in free_iommu()
1095 		free_page((unsigned long)iommu->qi->desc);  in free_iommu()
1096 		kfree(iommu->qi->desc_status);  in free_iommu()
1097 		kfree(iommu->qi);  in free_iommu()
1100 	if (iommu->reg)  in free_iommu()
1101 		unmap_iommu(iommu);  in free_iommu()
1103 	dmar_free_seq_id(iommu);  in free_iommu()
1104 	kfree(iommu);  in free_iommu()
1120 static int qi_check_fault(struct intel_iommu *iommu, int index)  in qi_check_fault()  argument
1124 	struct q_inval *qi = iommu->qi;  in qi_check_fault()
1130 	fault = readl(iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1138 		head = readl(iommu->reg + DMAR_IQH_REG);  in qi_check_fault()
1146 			__iommu_flush_cache(iommu, &qi->desc[index],  in qi_check_fault()
1148 			writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1158 		head = readl(iommu->reg + DMAR_IQH_REG);  in qi_check_fault()
1161 		tail = readl(iommu->reg + DMAR_IQT_REG);  in qi_check_fault()
1164 		writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1177 		writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1186 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)  in qi_submit_sync()  argument
1189 	struct q_inval *qi = iommu->qi;  in qi_submit_sync()
1222 	__iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc));  in qi_submit_sync()
1223 	__iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc));  in qi_submit_sync()
1232 	writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG);  in qi_submit_sync()
1242 		rc = qi_check_fault(iommu, index);  in qi_submit_sync()
1265 void qi_global_iec(struct intel_iommu *iommu)  in qi_global_iec()  argument
1273 	qi_submit_sync(&desc, iommu);  in qi_global_iec()
1276 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,  in qi_flush_context()  argument
1285 	qi_submit_sync(&desc, iommu);  in qi_flush_context()
1288 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,  in qi_flush_iotlb()  argument
1296 	if (cap_write_drain(iommu->cap))  in qi_flush_iotlb()
1299 	if (cap_read_drain(iommu->cap))  in qi_flush_iotlb()
1307 	qi_submit_sync(&desc, iommu);  in qi_flush_iotlb()
1310 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,  in qi_flush_dev_iotlb()  argument
1328 	qi_submit_sync(&desc, iommu);  in qi_flush_dev_iotlb()
1334 void dmar_disable_qi(struct intel_iommu *iommu)  in dmar_disable_qi()  argument
1340 	if (!ecap_qis(iommu->ecap))  in dmar_disable_qi()
1343 	raw_spin_lock_irqsave(&iommu->register_lock, flags);  in dmar_disable_qi()
1345 	sts =  readl(iommu->reg + DMAR_GSTS_REG);  in dmar_disable_qi()
1352 	while ((readl(iommu->reg + DMAR_IQT_REG) !=  in dmar_disable_qi()
1353 		readl(iommu->reg + DMAR_IQH_REG)) &&  in dmar_disable_qi()
1357 	iommu->gcmd &= ~DMA_GCMD_QIE;  in dmar_disable_qi()
1358 	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);  in dmar_disable_qi()
1360 	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,  in dmar_disable_qi()
1363 	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);  in dmar_disable_qi()
1369 static void __dmar_enable_qi(struct intel_iommu *iommu)  in __dmar_enable_qi()  argument
1373 	struct q_inval *qi = iommu->qi;  in __dmar_enable_qi()
1378 	raw_spin_lock_irqsave(&iommu->register_lock, flags);  in __dmar_enable_qi()
1381 	writel(0, iommu->reg + DMAR_IQT_REG);  in __dmar_enable_qi()
1383 	dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));  in __dmar_enable_qi()
1385 	iommu->gcmd |= DMA_GCMD_QIE;  in __dmar_enable_qi()
1386 	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);  in __dmar_enable_qi()
1389 	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);  in __dmar_enable_qi()
1391 	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);  in __dmar_enable_qi()
1399 int dmar_enable_qi(struct intel_iommu *iommu)  in dmar_enable_qi()  argument
1404 	if (!ecap_qis(iommu->ecap))  in dmar_enable_qi()
1410 	if (iommu->qi)  in dmar_enable_qi()
1413 	iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);  in dmar_enable_qi()
1414 	if (!iommu->qi)  in dmar_enable_qi()
1417 	qi = iommu->qi;  in dmar_enable_qi()
1420 	desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0);  in dmar_enable_qi()
1423 		iommu->qi = NULL;  in dmar_enable_qi()
1433 		iommu->qi = NULL;  in dmar_enable_qi()
1439 	__dmar_enable_qi(iommu);  in dmar_enable_qi()
1498 	struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);  in dmar_msi_unmask()  local
1502 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_unmask()
1503 	writel(0, iommu->reg + DMAR_FECTL_REG);  in dmar_msi_unmask()
1505 	readl(iommu->reg + DMAR_FECTL_REG);  in dmar_msi_unmask()
1506 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_unmask()
1512 	struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);  in dmar_msi_mask()  local
1515 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_mask()
1516 	writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);  in dmar_msi_mask()
1518 	readl(iommu->reg + DMAR_FECTL_REG);  in dmar_msi_mask()
1519 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_mask()
1524 	struct intel_iommu *iommu = irq_get_handler_data(irq);  in dmar_msi_write()  local
1527 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_write()
1528 	writel(msg->data, iommu->reg + DMAR_FEDATA_REG);  in dmar_msi_write()
1529 	writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);  in dmar_msi_write()
1530 	writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);  in dmar_msi_write()
1531 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_write()
1536 	struct intel_iommu *iommu = irq_get_handler_data(irq);  in dmar_msi_read()  local
1539 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_read()
1540 	msg->data = readl(iommu->reg + DMAR_FEDATA_REG);  in dmar_msi_read()
1541 	msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);  in dmar_msi_read()
1542 	msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);  in dmar_msi_read()
1543 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_read()
1546 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,  in dmar_fault_do_one()  argument
1574 	struct intel_iommu *iommu = dev_id;  in dmar_fault()  local
1579 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_fault()
1580 	fault_status = readl(iommu->reg + DMAR_FSTS_REG);  in dmar_fault()
1589 	reg = cap_fault_reg_offset(iommu->cap);  in dmar_fault()
1598 		data = readl(iommu->reg + reg +  in dmar_fault()
1606 		data = readl(iommu->reg + reg +  in dmar_fault()
1610 		guest_addr = dmar_readq(iommu->reg + reg +  in dmar_fault()
1614 		writel(DMA_FRCD_F, iommu->reg + reg +  in dmar_fault()
1617 		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_fault()
1619 		dmar_fault_do_one(iommu, type, fault_reason,  in dmar_fault()
1623 		if (fault_index >= cap_num_fault_regs(iommu->cap))  in dmar_fault()
1625 		raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_fault()
1628 	writel(DMA_FSTS_PFO | DMA_FSTS_PPF, iommu->reg + DMAR_FSTS_REG);  in dmar_fault()
1631 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_fault()
1635 int dmar_set_interrupt(struct intel_iommu *iommu)  in dmar_set_interrupt()  argument
1642 	if (iommu->irq)  in dmar_set_interrupt()
1651 	irq_set_handler_data(irq, iommu);  in dmar_set_interrupt()
1652 	iommu->irq = irq;  in dmar_set_interrupt()
1657 		iommu->irq = 0;  in dmar_set_interrupt()
1662 	ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);  in dmar_set_interrupt()
1671 	struct intel_iommu *iommu;  in enable_drhd_fault_handling()  local
1676 	for_each_iommu(iommu, drhd) {  in enable_drhd_fault_handling()
1678 		int ret = dmar_set_interrupt(iommu);  in enable_drhd_fault_handling()
1689 		dmar_fault(iommu->irq, iommu);  in enable_drhd_fault_handling()
1690 		fault_status = readl(iommu->reg + DMAR_FSTS_REG);  in enable_drhd_fault_handling()
1691 		writel(fault_status, iommu->reg + DMAR_FSTS_REG);  in enable_drhd_fault_handling()
1700 int dmar_reenable_qi(struct intel_iommu *iommu)  in dmar_reenable_qi()  argument
1702 	if (!ecap_qis(iommu->ecap))  in dmar_reenable_qi()
1705 	if (!iommu->qi)  in dmar_reenable_qi()
1711 	dmar_disable_qi(iommu);  in dmar_reenable_qi()
1717 	__dmar_enable_qi(iommu);  in dmar_reenable_qi()