104 		writel(hwirq, main_int_base +  in armada_370_xp_irq_mask()
107 		writel(hwirq, per_cpu_int_base +  in armada_370_xp_irq_mask()
116 		writel(hwirq, main_int_base +  in armada_370_xp_irq_unmask()
119 		writel(hwirq, per_cpu_int_base +  in armada_370_xp_irq_unmask()
250 	writel(reg, per_cpu_int_base +  in armada_370_xp_msi_init()
254 	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_370_xp_msi_init()
283 	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));  in armada_xp_set_affinity()
306 		writel(hw, per_cpu_int_base +  in armada_370_xp_mpic_irq_map()
309 		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);  in armada_370_xp_mpic_irq_map()
335 		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);  in armada_xp_mpic_smp_cpu_init()
338 	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);  in armada_xp_mpic_smp_cpu_init()
341 	writel(IPI_DOORBELL_MASK, per_cpu_int_base +  in armada_xp_mpic_smp_cpu_init()
345 	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_xp_mpic_smp_cpu_init()
353 	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),  in armada_xp_mpic_perf_init()
375 	writel((map << 8) | irq, main_int_base +  in armada_mpic_send_doorbell()
426 	writel(~msimask, per_cpu_int_base +  in armada_370_xp_handle_msi_irq()
517 			writel(~ipimask, per_cpu_int_base +  in armada_370_xp_handle_irq()
556 			writel(irq, per_cpu_int_base +  in armada_370_xp_mpic_resume()
559 			writel(irq, main_int_base +  in armada_370_xp_mpic_resume()
568 	writel(doorbell_mask_reg,  in armada_370_xp_mpic_resume()
571 		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_370_xp_mpic_resume()
573 		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_370_xp_mpic_resume()
610 		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);  in armada_370_xp_mpic_of_init()