73 	struct irq_domain_chip_generic *dgc = aic5_domain->gc;  in aic5_handle()
74 	struct irq_chip_generic *gc = dgc->gc[0];  in aic5_handle()  local
78 	irqnr = irq_reg_readl(gc, AT91_AIC5_IVR);  in aic5_handle()
79 	irqstat = irq_reg_readl(gc, AT91_AIC5_ISR);  in aic5_handle()
82 		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);  in aic5_handle()
90 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_mask()
91 	struct irq_chip_generic *bgc = dgc->gc[0];  in aic5_mask()
92 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_mask()  local
99 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_mask()
100 	irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_mask()
101 	gc->mask_cache &= ~d->mask;  in aic5_mask()
108 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_unmask()
109 	struct irq_chip_generic *bgc = dgc->gc[0];  in aic5_unmask()
110 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_unmask()  local
117 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_unmask()
118 	irq_reg_writel(gc, 1, AT91_AIC5_IECR);  in aic5_unmask()
119 	gc->mask_cache |= d->mask;  in aic5_unmask()
126 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_retrigger()
127 	struct irq_chip_generic *gc = dgc->gc[0];  in aic5_retrigger()  local
130 	irq_gc_lock(gc);  in aic5_retrigger()
131 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_retrigger()
132 	irq_reg_writel(gc, 1, AT91_AIC5_ISCR);  in aic5_retrigger()
133 	irq_gc_unlock(gc);  in aic5_retrigger()
141 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_set_type()
142 	struct irq_chip_generic *gc = dgc->gc[0];  in aic5_set_type()  local
146 	irq_gc_lock(gc);  in aic5_set_type()
147 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_set_type()
148 	smr = irq_reg_readl(gc, AT91_AIC5_SMR);  in aic5_set_type()
151 		irq_reg_writel(gc, smr, AT91_AIC5_SMR);  in aic5_set_type()
152 	irq_gc_unlock(gc);  in aic5_set_type()
161 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_suspend()
162 	struct irq_chip_generic *bgc = dgc->gc[0];  in aic5_suspend()
163 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_suspend()  local
170 		if ((mask & gc->mask_cache) == (mask & gc->wake_active))  in aic5_suspend()
173 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_suspend()
174 		if (mask & gc->wake_active)  in aic5_suspend()
185 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_resume()
186 	struct irq_chip_generic *bgc = dgc->gc[0];  in aic5_resume()
187 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_resume()  local
194 		if ((mask & gc->mask_cache) == (mask & gc->wake_active))  in aic5_resume()
197 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_resume()
198 		if (mask & gc->mask_cache)  in aic5_resume()
209 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_pm_shutdown()
210 	struct irq_chip_generic *bgc = dgc->gc[0];  in aic5_pm_shutdown()
211 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_pm_shutdown()  local
216 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_pm_shutdown()
230 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);  in aic5_hw_init()  local
238 		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);  in aic5_hw_init()
245 	irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);  in aic5_hw_init()
248 	irq_reg_writel(gc, 0, AT91_AIC5_DCR);  in aic5_hw_init()
252 		irq_reg_writel(gc, i, AT91_AIC5_SSR);  in aic5_hw_init()
253 		irq_reg_writel(gc, i, AT91_AIC5_SVR);  in aic5_hw_init()
254 		irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_hw_init()
255 		irq_reg_writel(gc, 1, AT91_AIC5_ICCR);  in aic5_hw_init()
265 	struct irq_domain_chip_generic *dgc = d->gc;  in aic5_irq_domain_xlate()
266 	struct irq_chip_generic *gc;  in aic5_irq_domain_xlate()  local
278 	gc = dgc->gc[0];  in aic5_irq_domain_xlate()
280 	irq_gc_lock(gc);  in aic5_irq_domain_xlate()
281 	irq_reg_writel(gc, *out_hwirq, AT91_AIC5_SSR);  in aic5_irq_domain_xlate()
282 	smr = irq_reg_readl(gc, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()
285 		irq_reg_writel(gc, intspec[2] | smr, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()
286 	irq_gc_unlock(gc);  in aic5_irq_domain_xlate()
311 	struct irq_chip_generic *gc;  in aic5_of_init()  local
332 		gc = irq_get_domain_generic_chip(domain, i * 32);  in aic5_of_init()
334 		gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;  in aic5_of_init()
335 		gc->chip_types[0].chip.irq_mask = aic5_mask;  in aic5_of_init()
336 		gc->chip_types[0].chip.irq_unmask = aic5_unmask;  in aic5_of_init()
337 		gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;  in aic5_of_init()
338 		gc->chip_types[0].chip.irq_set_type = aic5_set_type;  in aic5_of_init()
339 		gc->chip_types[0].chip.irq_suspend = aic5_suspend;  in aic5_of_init()
340 		gc->chip_types[0].chip.irq_resume = aic5_resume;  in aic5_of_init()
341 		gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;  in aic5_of_init()