82 		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);  in aic5_handle()
99 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_mask()
100 	irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_mask()
117 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_unmask()
118 	irq_reg_writel(gc, 1, AT91_AIC5_IECR);  in aic5_unmask()
131 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_retrigger()
132 	irq_reg_writel(gc, 1, AT91_AIC5_ISCR);  in aic5_retrigger()
147 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_set_type()
151 		irq_reg_writel(gc, smr, AT91_AIC5_SMR);  in aic5_set_type()
173 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_suspend()
175 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_suspend()
177 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_suspend()
197 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_resume()
199 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_resume()
201 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_resume()
216 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_pm_shutdown()
217 		irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_pm_shutdown()
218 		irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);  in aic5_pm_shutdown()
238 		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);  in aic5_hw_init()
245 	irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);  in aic5_hw_init()
248 	irq_reg_writel(gc, 0, AT91_AIC5_DCR);  in aic5_hw_init()
252 		irq_reg_writel(gc, i, AT91_AIC5_SSR);  in aic5_hw_init()
253 		irq_reg_writel(gc, i, AT91_AIC5_SVR);  in aic5_hw_init()
254 		irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_hw_init()
255 		irq_reg_writel(gc, 1, AT91_AIC5_ICCR);  in aic5_hw_init()
281 	irq_reg_writel(gc, *out_hwirq, AT91_AIC5_SSR);  in aic5_irq_domain_xlate()
285 		irq_reg_writel(gc, intspec[2] | smr, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()