32 	struct irq_chip_generic *gc = irq_get_handler_data(irq);  in dw_apb_ictl_handler()  local
33 	struct irq_domain *d = gc->private;  in dw_apb_ictl_handler()
39 	for (n = 0; n < gc->num_ct; n++) {  in dw_apb_ictl_handler()
40 		stat = readl_relaxed(gc->reg_base +  in dw_apb_ictl_handler()
45 					    gc->irq_base + hwirq + 32 * n));  in dw_apb_ictl_handler()
56 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in dw_apb_ictl_resume()  local
59 	irq_gc_lock(gc);  in dw_apb_ictl_resume()
60 	writel_relaxed(~0, gc->reg_base + ct->regs.enable);  in dw_apb_ictl_resume()
61 	writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);  in dw_apb_ictl_resume()
62 	irq_gc_unlock(gc);  in dw_apb_ictl_resume()
74 	struct irq_chip_generic *gc;  in dw_apb_ictl_init()  local
140 	gc = irq_get_domain_generic_chip(domain, 0);  in dw_apb_ictl_init()
141 	gc->private = domain;  in dw_apb_ictl_init()
142 	gc->reg_base = iobase;  in dw_apb_ictl_init()
144 	gc->chip_types[0].regs.mask = APB_INT_MASK_L;  in dw_apb_ictl_init()
145 	gc->chip_types[0].regs.enable = APB_INT_ENABLE_L;  in dw_apb_ictl_init()
146 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;  in dw_apb_ictl_init()
147 	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;  in dw_apb_ictl_init()
148 	gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;  in dw_apb_ictl_init()
151 		gc->chip_types[1].regs.mask = APB_INT_MASK_H;  in dw_apb_ictl_init()
152 		gc->chip_types[1].regs.enable = APB_INT_ENABLE_H;  in dw_apb_ictl_init()
153 		gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;  in dw_apb_ictl_init()
154 		gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;  in dw_apb_ictl_init()
155 		gc->chip_types[1].chip.irq_resume = dw_apb_ictl_resume;  in dw_apb_ictl_init()
158 	irq_set_handler_data(irq, gc);  in dw_apb_ictl_init()