Lines Matching refs:writel
106 writel(VIC_VECT_CNTL_ENABLE | i, reg); in vic_init2()
109 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2()
122 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
123 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic()
126 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic()
127 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); in resume_one_vic()
131 writel(vic->soft_int, base + VIC_INT_SOFT); in resume_one_vic()
132 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); in resume_one_vic()
157 writel(vic->resume_irqs, base + VIC_INT_ENABLE); in suspend_one_vic()
158 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); in suspend_one_vic()
321 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); in vic_ack_irq()
323 writel(1 << irq, base + VIC_INT_SOFT_CLEAR); in vic_ack_irq()
330 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); in vic_mask_irq()
337 writel(1 << irq, base + VIC_INT_ENABLE); in vic_unmask_irq()
388 writel(0, base + VIC_INT_SELECT); in vic_disable()
389 writel(0, base + VIC_INT_ENABLE); in vic_disable()
390 writel(~0, base + VIC_INT_ENABLE_CLEAR); in vic_disable()
391 writel(0, base + VIC_ITCR); in vic_disable()
392 writel(~0, base + VIC_INT_SOFT_CLEAR); in vic_disable()
399 writel(0, base + VIC_PL190_VECT_ADDR); in vic_clear_interrupts()
404 writel(value, base + VIC_PL190_VECT_ADDR); in vic_clear_interrupts()
436 writel(0, reg); in vic_init_st()
439 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init_st()