691 	const struct dibx000_bandwidth_config *pll = state->cfg.pll;  in dib8000_reset_pll()  local
696 				(pll->pll_prediv << 8) | (pll->pll_ratio << 0));  in dib8000_reset_pll()
698 		clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |  in dib8000_reset_pll()
699 			(pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |  in dib8000_reset_pll()
700 			(1 << 3) | (pll->pll_range << 1) |  in dib8000_reset_pll()
701 			(pll->pll_reset << 0);  in dib8000_reset_pll()
704 		clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);  in dib8000_reset_pll()
710 		if (state->cfg.pll->ADClkSrc == 0)  in dib8000_reset_pll()
713 					(pll->modulo << 8) |  in dib8000_reset_pll()
714 					(pll->ADClkSrc << 7) | (0 << 1));  in dib8000_reset_pll()
718 					(pll->modulo << 8) |  in dib8000_reset_pll()
719 					(pll->ADClkSrc << 7) | (0 << 1));  in dib8000_reset_pll()
722 					(3 << 10) | (pll->modulo << 8) |  in dib8000_reset_pll()
723 					(pll->ADClkSrc << 7) | (0 << 1));  in dib8000_reset_pll()
725 		dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |  in dib8000_reset_pll()
726 				(pll->pll_range<<12) | (pll->pll_ratio<<6) |  in dib8000_reset_pll()
727 				(pll->pll_prediv));  in dib8000_reset_pll()
730 		dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));  in dib8000_reset_pll()
735 		dib8000_write_word(state, 904, (pll->modulo << 8));  in dib8000_reset_pll()
738 	dib8000_reset_pll_common(state, pll);  in dib8000_reset_pll()
742 		struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio)  in dib8000_update_pll()  argument
746 	u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;  in dib8000_update_pll()
753 	if ((pll == NULL) || (pll->pll_prediv == prediv &&  in dib8000_update_pll()
754 				pll->pll_ratio == loopdiv))  in dib8000_update_pll()
757 …: old =  %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_r…  in dib8000_update_pll()
765 				((pll->pll_ratio & 0x3f) << 6) |  in dib8000_update_pll()
766 				(pll->pll_prediv & 0x3f));  in dib8000_update_pll()
772 		internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;  in dib8000_update_pll()
792 …rediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);  in dib8000_update_pll()
794 			if (state->cfg.pll->pll_prediv != oldprediv) {  in dib8000_update_pll()
798 … MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_…  in dib8000_update_pll()
803 				ratio = state->cfg.pll->pll_ratio;  in dib8000_update_pll()
810 			dprintk("PLL: Update ratio (prediv: %d, ratio: %d)", state->cfg.pll->pll_prediv, ratio);  in dib8000_update_pll()
811 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL …  in dib8000_update_pll()
1093 	if (state->cfg.pll->ifreq == 0)  in dib8000_reset()
2168 	if (state->cfg.pll->ifreq == 0)  in dib8000_set_13seg_channel()
2493 	u32 value, internal = state->cfg.pll->internal;  in dib8000_autosearch_start()
2674 	u32 dds = state->cfg.pll->ifreq & 0x1ffffff;  in dib8000_set_dds()
2675 	u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));  in dib8000_set_dds()
2690 		unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);  in dib8000_set_dds()
2704 	if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {  in dib8000_set_dds()
2732 		if (state->cfg.pll->ifreq == 0) { /* low if tuner */  in dib8000_set_frequency_offset()
4462 	state->timf_default = cfg->pll->timf;  in dib8000_init()