Lines Matching defs:drxj_data
407 struct drxj_data { struct
409 bool has_lna; /**< true if LNA (aka PGA) present */
410 bool has_oob; /**< true if OOB supported */
411 bool has_ntsc; /**< true if NTSC supported */
412 bool has_btsc; /**< true if BTSC supported */
413 bool has_smatx; /**< true if mat_tx is available */
414 bool has_smarx; /**< true if mat_rx is available */
415 bool has_gpio; /**< true if GPIO is available */
416 bool has_irqn; /**< true if IRQN is available */
418 u8 mfx; /**< metal fix */
421 bool mirror_freq_spect_oob;/**< tuner inversion (true = tuner mirrors the signal */
424 enum drx_standard standard; /**< current standard information */
425 enum drx_modulation constellation;
427 s32 frequency; /**< center signal frequency in KHz */
428 enum drx_bandwidth curr_bandwidth;
430 enum drx_mirror mirror; /**< current channel mirror */
433 u32 fec_bits_desired; /**< BER accounting period */
434 u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */
435 u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */
436 u16 qam_vd_period; /**< Viterbi Measurement period */
437 u16 fec_rs_plen; /**< defines RS BER measurement period */
438 u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */
439 u16 fec_rs_period; /**< ReedSolomon Measurement period */
440 bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */
441 u16 pkt_err_acc_start; /**< Set a flag to reset accumulated packet error */
444 u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */
445 u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */
446 u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */
447 u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */
448 u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */
451 enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */
452 enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */
453 enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */
454 enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */
457 u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */
458 bool pos_image; /**< Ture: positive image */
460 u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */
463 u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */
464 s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
465 s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
466 s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
467 s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
468 bool phase_correction_bypass;/**< flag: true=bypass */
469 s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */
470 u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */
471 bool enable_cvbs_output; /**< flag CVBS ouput enable */
472 bool enable_sif_output; /**< flag SIF ouput enable */
473 enum drxjsif_attenuation sif_attenuation;
476 struct drxj_cfg_agc qam_rf_agc_cfg; /**< qam RF AGC config */
477 struct drxj_cfg_agc qam_if_agc_cfg; /**< qam IF AGC config */
478 struct drxj_cfg_agc vsb_rf_agc_cfg; /**< vsb RF AGC config */
479 struct drxj_cfg_agc vsb_if_agc_cfg; /**< vsb IF AGC config */
482 u16 qam_pga_cfg; /**< qam PGA config */
483 u16 vsb_pga_cfg; /**< vsb PGA config */
486 struct drxj_cfg_pre_saw qam_pre_saw_cfg;
488 struct drxj_cfg_pre_saw vsb_pre_saw_cfg;
492 char v_text[2][12]; /**< allocated text versions */
493 struct drx_version v_version[2]; /**< allocated versions structs */
494 struct drx_version_list v_list_elements[2];
498 bool smart_ant_inverted;
501 u16 oob_trk_filter_cfg[8];
502 bool oob_power_on;
505 u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */
506 bool disable_te_ihandling; /**< MPEG TS TEI handling */
507 bool bit_reverse_mpeg_outout;/**< MPEG output bit order */
508 enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
510 enum drxj_mpeg_start_width mpeg_start_width;
514 struct drxj_cfg_pre_saw atv_pre_saw_cfg;
516 struct drxj_cfg_agc atv_rf_agc_cfg; /**< atv RF AGC config */
517 struct drxj_cfg_agc atv_if_agc_cfg; /**< atv IF AGC config */
518 u16 atv_pga_cfg; /**< atv pga config */
520 u32 curr_symbol_rate;
523 bool pdr_safe_mode; /**< PDR safe mode activated */
524 u16 pdr_safe_restore_val_gpio;
525 u16 pdr_safe_restore_val_v_sync;
526 u16 pdr_safe_restore_val_sma_rx;
527 u16 pdr_safe_restore_val_sma_tx;
551 (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) argument