Lines Matching refs:val
117 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) in lgdt3306a_write_reg() argument
120 u8 buf[] = { reg >> 8, reg & 0xff, val }; in lgdt3306a_write_reg()
126 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); in lgdt3306a_write_reg()
141 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) in lgdt3306a_read_reg() argument
149 .flags = I2C_M_RD, .buf = val, .len = 1 }, in lgdt3306a_read_reg()
162 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); in lgdt3306a_read_reg()
179 u8 val; in lgdt3306a_set_reg_bit() local
184 ret = lgdt3306a_read_reg(state, reg, &val); in lgdt3306a_set_reg_bit()
188 val &= ~(1 << bit); in lgdt3306a_set_reg_bit()
189 val |= (onoff & 1) << bit; in lgdt3306a_set_reg_bit()
191 ret = lgdt3306a_write_reg(state, reg, val); in lgdt3306a_set_reg_bit()
220 u8 val; in lgdt3306a_mpeg_mode() local
238 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_mode()
242 val |= 0x10; /* TPCLKSUPB=0x10 */ in lgdt3306a_mpeg_mode()
245 val &= ~0x10; in lgdt3306a_mpeg_mode()
247 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_mode()
258 u8 val; in lgdt3306a_mpeg_mode_polarity() local
263 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_mode_polarity()
267 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */ in lgdt3306a_mpeg_mode_polarity()
270 val |= 0x04; in lgdt3306a_mpeg_mode_polarity()
272 val |= 0x02; in lgdt3306a_mpeg_mode_polarity()
274 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_mode_polarity()
284 u8 val; in lgdt3306a_mpeg_tristate() local
290 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_tristate()
297 val &= ~0xa8; in lgdt3306a_mpeg_tristate()
298 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_tristate()
313 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_tristate()
317 val |= 0xa8; /* enable bus */ in lgdt3306a_mpeg_tristate()
318 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_tristate()
377 u8 val; in lgdt3306a_set_vsb() local
383 ret = lgdt3306a_read_reg(state, 0x0002, &val); in lgdt3306a_set_vsb()
384 val &= 0xf7; /* SPECINVAUTO Off */ in lgdt3306a_set_vsb()
385 val |= 0x04; /* SPECINV On */ in lgdt3306a_set_vsb()
386 ret = lgdt3306a_write_reg(state, 0x0002, val); in lgdt3306a_set_vsb()
396 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_vsb()
397 val &= 0xe3; in lgdt3306a_set_vsb()
398 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */ in lgdt3306a_set_vsb()
399 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_vsb()
404 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_vsb()
405 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */ in lgdt3306a_set_vsb()
406 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_vsb()
411 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_set_vsb()
412 val &= 0xbf; /* SAMPLING4XFEN=0 */ in lgdt3306a_set_vsb()
413 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_set_vsb()
473 ret = lgdt3306a_read_reg(state, 0x001e, &val); in lgdt3306a_set_vsb()
474 val &= 0x0f; in lgdt3306a_set_vsb()
475 val |= 0xa0; in lgdt3306a_set_vsb()
476 ret = lgdt3306a_write_reg(state, 0x001e, val); in lgdt3306a_set_vsb()
482 ret = lgdt3306a_read_reg(state, 0x211f, &val); in lgdt3306a_set_vsb()
483 val &= 0xef; in lgdt3306a_set_vsb()
484 ret = lgdt3306a_write_reg(state, 0x211f, val); in lgdt3306a_set_vsb()
488 ret = lgdt3306a_read_reg(state, 0x1061, &val); in lgdt3306a_set_vsb()
489 val &= 0xf8; in lgdt3306a_set_vsb()
490 val |= 0x04; in lgdt3306a_set_vsb()
491 ret = lgdt3306a_write_reg(state, 0x1061, val); in lgdt3306a_set_vsb()
493 ret = lgdt3306a_read_reg(state, 0x103d, &val); in lgdt3306a_set_vsb()
494 val &= 0xcf; in lgdt3306a_set_vsb()
495 ret = lgdt3306a_write_reg(state, 0x103d, val); in lgdt3306a_set_vsb()
499 ret = lgdt3306a_read_reg(state, 0x2141, &val); in lgdt3306a_set_vsb()
500 val &= 0x3f; in lgdt3306a_set_vsb()
501 ret = lgdt3306a_write_reg(state, 0x2141, val); in lgdt3306a_set_vsb()
503 ret = lgdt3306a_read_reg(state, 0x2135, &val); in lgdt3306a_set_vsb()
504 val &= 0x0f; in lgdt3306a_set_vsb()
505 val |= 0x70; in lgdt3306a_set_vsb()
506 ret = lgdt3306a_write_reg(state, 0x2135, val); in lgdt3306a_set_vsb()
508 ret = lgdt3306a_read_reg(state, 0x0003, &val); in lgdt3306a_set_vsb()
509 val &= 0xf7; in lgdt3306a_set_vsb()
510 ret = lgdt3306a_write_reg(state, 0x0003, val); in lgdt3306a_set_vsb()
512 ret = lgdt3306a_read_reg(state, 0x001c, &val); in lgdt3306a_set_vsb()
513 val &= 0x7f; in lgdt3306a_set_vsb()
514 ret = lgdt3306a_write_reg(state, 0x001c, val); in lgdt3306a_set_vsb()
517 ret = lgdt3306a_read_reg(state, 0x2179, &val); in lgdt3306a_set_vsb()
518 val &= 0xf8; in lgdt3306a_set_vsb()
519 ret = lgdt3306a_write_reg(state, 0x2179, val); in lgdt3306a_set_vsb()
521 ret = lgdt3306a_read_reg(state, 0x217a, &val); in lgdt3306a_set_vsb()
522 val &= 0xf8; in lgdt3306a_set_vsb()
523 ret = lgdt3306a_write_reg(state, 0x217a, val); in lgdt3306a_set_vsb()
537 u8 val; in lgdt3306a_set_qam() local
548 ret = lgdt3306a_read_reg(state, 0x0002, &val); in lgdt3306a_set_qam()
549 val &= 0xfb; /* SPECINV Off */ in lgdt3306a_set_qam()
550 val |= 0x08; /* SPECINVAUTO On */ in lgdt3306a_set_qam()
551 ret = lgdt3306a_write_reg(state, 0x0002, val); in lgdt3306a_set_qam()
556 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_qam()
557 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */ in lgdt3306a_set_qam()
558 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_qam()
563 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_qam()
564 val &= 0xfc; in lgdt3306a_set_qam()
565 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */ in lgdt3306a_set_qam()
566 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_qam()
571 ret = lgdt3306a_read_reg(state, 0x101a, &val); in lgdt3306a_set_qam()
572 val &= 0xf8; in lgdt3306a_set_qam()
574 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */ in lgdt3306a_set_qam()
576 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */ in lgdt3306a_set_qam()
578 ret = lgdt3306a_write_reg(state, 0x101a, val); in lgdt3306a_set_qam()
583 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_set_qam()
584 val &= 0xbf; in lgdt3306a_set_qam()
585 val |= 0x40; /* SAMPLING4XFEN=1 */ in lgdt3306a_set_qam()
586 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_set_qam()
591 ret = lgdt3306a_read_reg(state, 0x0024, &val); in lgdt3306a_set_qam()
592 val &= 0x00; in lgdt3306a_set_qam()
593 ret = lgdt3306a_write_reg(state, 0x0024, val); in lgdt3306a_set_qam()
814 u8 val; in lgdt3306a_init() local
864 ret = lgdt3306a_read_reg(state, 0x0005, &val); in lgdt3306a_init()
867 val &= 0xc0; in lgdt3306a_init()
868 val |= 0x25; in lgdt3306a_init()
869 ret = lgdt3306a_write_reg(state, 0x0005, val); in lgdt3306a_init()
877 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_init()
880 val &= 0xc0; in lgdt3306a_init()
881 val |= 0x18; in lgdt3306a_init()
882 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_init()
888 ret = lgdt3306a_read_reg(state, 0x0005, &val); in lgdt3306a_init()
891 val &= 0xc0; in lgdt3306a_init()
892 val |= 0x25; in lgdt3306a_init()
893 ret = lgdt3306a_write_reg(state, 0x0005, val); in lgdt3306a_init()
901 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_init()
904 val &= 0xc0; in lgdt3306a_init()
905 val |= 0x19; in lgdt3306a_init()
906 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_init()
925 ret = lgdt3306a_read_reg(state, 0x103c, &val); in lgdt3306a_init()
926 val &= 0x0f; in lgdt3306a_init()
927 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */ in lgdt3306a_init()
928 ret = lgdt3306a_write_reg(state, 0x103c, val); in lgdt3306a_init()
931 ret = lgdt3306a_read_reg(state, 0x103d, &val); in lgdt3306a_init()
932 val &= 0xfc; in lgdt3306a_init()
933 val |= 0x03; in lgdt3306a_init()
934 ret = lgdt3306a_write_reg(state, 0x103d, val); in lgdt3306a_init()
937 ret = lgdt3306a_read_reg(state, 0x1036, &val); in lgdt3306a_init()
938 val &= 0xf0; in lgdt3306a_init()
939 val |= 0x0c; in lgdt3306a_init()
940 ret = lgdt3306a_write_reg(state, 0x1036, val); in lgdt3306a_init()
943 ret = lgdt3306a_read_reg(state, 0x211f, &val); in lgdt3306a_init()
944 val &= 0xef; /* do not use imaginary of CIR */ in lgdt3306a_init()
945 ret = lgdt3306a_write_reg(state, 0x211f, val); in lgdt3306a_init()
948 ret = lgdt3306a_read_reg(state, 0x2849, &val); in lgdt3306a_init()
949 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */ in lgdt3306a_init()
950 ret = lgdt3306a_write_reg(state, 0x2849, val); in lgdt3306a_init()
1068 u8 val; in lgdt3306a_monitor_vsb() local
1073 ret = lgdt3306a_read_reg(state, 0x21a1, &val); in lgdt3306a_monitor_vsb()
1076 snrRef = val & 0x3f; in lgdt3306a_monitor_vsb()
1082 ret = lgdt3306a_read_reg(state, 0x2191, &val); in lgdt3306a_monitor_vsb()
1085 nCombDet = (val & 0x80) >> 7; in lgdt3306a_monitor_vsb()
1087 ret = lgdt3306a_read_reg(state, 0x2180, &val); in lgdt3306a_monitor_vsb()
1090 fbDlyCir = (val & 0x03) << 8; in lgdt3306a_monitor_vsb()
1092 ret = lgdt3306a_read_reg(state, 0x2181, &val); in lgdt3306a_monitor_vsb()
1095 fbDlyCir |= val; in lgdt3306a_monitor_vsb()
1101 ret = lgdt3306a_read_reg(state, 0x1061, &val); in lgdt3306a_monitor_vsb()
1104 val &= 0xf8; in lgdt3306a_monitor_vsb()
1109 val |= 0x00; /* final bandwidth = 0 */ in lgdt3306a_monitor_vsb()
1111 val |= 0x04; /* final bandwidth = 4 */ in lgdt3306a_monitor_vsb()
1113 ret = lgdt3306a_write_reg(state, 0x1061, val); in lgdt3306a_monitor_vsb()
1118 ret = lgdt3306a_read_reg(state, 0x0024, &val); in lgdt3306a_monitor_vsb()
1121 val &= 0x0f; in lgdt3306a_monitor_vsb()
1123 val |= 0x50; in lgdt3306a_monitor_vsb()
1125 ret = lgdt3306a_write_reg(state, 0x0024, val); in lgdt3306a_monitor_vsb()
1130 ret = lgdt3306a_read_reg(state, 0x103d, &val); in lgdt3306a_monitor_vsb()
1133 val &= 0xcf; in lgdt3306a_monitor_vsb()
1134 val |= 0x20; in lgdt3306a_monitor_vsb()
1135 ret = lgdt3306a_write_reg(state, 0x103d, val); in lgdt3306a_monitor_vsb()
1143 u8 val = 0; in lgdt3306a_check_oper_mode() local
1146 ret = lgdt3306a_read_reg(state, 0x0081, &val); in lgdt3306a_check_oper_mode()
1150 if (val & 0x80) { in lgdt3306a_check_oper_mode()
1154 if (val & 0x08) { in lgdt3306a_check_oper_mode()
1155 ret = lgdt3306a_read_reg(state, 0x00a6, &val); in lgdt3306a_check_oper_mode()
1158 val = val >> 2; in lgdt3306a_check_oper_mode()
1159 if (val & 0x01) { in lgdt3306a_check_oper_mode()
1175 u8 val = 0; in lgdt3306a_check_lock_status() local
1185 ret = lgdt3306a_read_reg(state, 0x00a6, &val); in lgdt3306a_check_lock_status()
1189 if ((val & 0x80) == 0x80) in lgdt3306a_check_lock_status()
1199 ret = lgdt3306a_read_reg(state, 0x0080, &val); in lgdt3306a_check_lock_status()
1203 if ((val & 0x40) == 0x40) in lgdt3306a_check_lock_status()
1215 ret = lgdt3306a_read_reg(state, 0x1094, &val); in lgdt3306a_check_lock_status()
1219 if ((val & 0x80) == 0x80) in lgdt3306a_check_lock_status()
1233 ret = lgdt3306a_read_reg(state, 0x0080, &val); in lgdt3306a_check_lock_status()
1237 if ((val & 0x10) == 0x10) in lgdt3306a_check_lock_status()
1260 u8 val = 0; in lgdt3306a_check_neverlock_status() local
1264 ret = lgdt3306a_read_reg(state, 0x0080, &val); in lgdt3306a_check_neverlock_status()
1267 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03); in lgdt3306a_check_neverlock_status()
1276 u8 val = 0; in lgdt3306a_pre_monitoring() local
1286 ret = lgdt3306a_read_reg(state, 0x21a1, &val); in lgdt3306a_pre_monitoring()
1289 snrRef = val & 0x3f; in lgdt3306a_pre_monitoring()
1292 ret = lgdt3306a_read_reg(state, 0x2199, &val); in lgdt3306a_pre_monitoring()
1295 mainStrong = (val & 0x40) >> 6; in lgdt3306a_pre_monitoring()
1297 ret = lgdt3306a_read_reg(state, 0x0090, &val); in lgdt3306a_pre_monitoring()
1300 aiccrejStatus = (val & 0xf0) >> 4; in lgdt3306a_pre_monitoring()
1310 ret = lgdt3306a_read_reg(state, 0x2135, &val); in lgdt3306a_pre_monitoring()
1313 val &= 0x0f; in lgdt3306a_pre_monitoring()
1314 val |= 0xa0; in lgdt3306a_pre_monitoring()
1315 ret = lgdt3306a_write_reg(state, 0x2135, val); in lgdt3306a_pre_monitoring()
1319 ret = lgdt3306a_read_reg(state, 0x2141, &val); in lgdt3306a_pre_monitoring()
1322 val &= 0x3f; in lgdt3306a_pre_monitoring()
1323 val |= 0x80; in lgdt3306a_pre_monitoring()
1324 ret = lgdt3306a_write_reg(state, 0x2141, val); in lgdt3306a_pre_monitoring()
1332 ret = lgdt3306a_read_reg(state, 0x2135, &val); in lgdt3306a_pre_monitoring()
1335 val &= 0x0f; in lgdt3306a_pre_monitoring()
1336 val |= 0x70; in lgdt3306a_pre_monitoring()
1337 ret = lgdt3306a_write_reg(state, 0x2135, val); in lgdt3306a_pre_monitoring()
1341 ret = lgdt3306a_read_reg(state, 0x2141, &val); in lgdt3306a_pre_monitoring()
1344 val &= 0x3f; in lgdt3306a_pre_monitoring()
1345 val |= 0x40; in lgdt3306a_pre_monitoring()
1346 ret = lgdt3306a_write_reg(state, 0x2141, val); in lgdt3306a_pre_monitoring()
1421 u8 val; in lgdt3306a_get_packet_error() local
1424 ret = lgdt3306a_read_reg(state, 0x00fa, &val); in lgdt3306a_get_packet_error()
1428 return val; in lgdt3306a_get_packet_error()
1784 u8 val; in lgdt3306a_attach() local
1804 ret = lgdt3306a_read_reg(state, 0x0000, &val); in lgdt3306a_attach()
1807 if ((val & 0x74) != 0x74) { in lgdt3306a_attach()
1808 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74)); in lgdt3306a_attach()
1814 ret = lgdt3306a_read_reg(state, 0x0001, &val); in lgdt3306a_attach()
1817 if ((val & 0xf6) != 0xc6) { in lgdt3306a_attach()
1818 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6)); in lgdt3306a_attach()
1824 ret = lgdt3306a_read_reg(state, 0x0002, &val); in lgdt3306a_attach()
1827 if ((val & 0x73) != 0x03) { in lgdt3306a_attach()
1828 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73)); in lgdt3306a_attach()