Lines Matching refs:ret
66 int ret; in mt312_read() local
79 ret = i2c_transfer(state->i2c, msg, 2); in mt312_read()
81 if (ret != 2) { in mt312_read()
82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); in mt312_read()
100 int ret; in mt312_write() local
126 ret = i2c_transfer(state->i2c, &msg, 1); in mt312_write()
128 if (ret != 1) { in mt312_write()
129 dprintk("%s: ret == %d\n", __func__, ret); in mt312_write()
161 int ret; in mt312_get_inversion() local
164 ret = mt312_readreg(state, VIT_MODE, &vit_mode); in mt312_get_inversion()
165 if (ret < 0) in mt312_get_inversion()
166 return ret; in mt312_get_inversion()
176 int ret; in mt312_get_symbol_rate() local
183 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); in mt312_get_symbol_rate()
184 if (ret < 0) in mt312_get_symbol_rate()
185 return ret; in mt312_get_symbol_rate()
189 ret = mt312_writereg(state, MON_CTRL, 0x03); in mt312_get_symbol_rate()
190 if (ret < 0) in mt312_get_symbol_rate()
191 return ret; in mt312_get_symbol_rate()
193 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
194 if (ret < 0) in mt312_get_symbol_rate()
195 return ret; in mt312_get_symbol_rate()
202 ret = mt312_writereg(state, MON_CTRL, 0x05); in mt312_get_symbol_rate()
203 if (ret < 0) in mt312_get_symbol_rate()
204 return ret; in mt312_get_symbol_rate()
206 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
207 if (ret < 0) in mt312_get_symbol_rate()
208 return ret; in mt312_get_symbol_rate()
212 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
213 if (ret < 0) in mt312_get_symbol_rate()
214 return ret; in mt312_get_symbol_rate()
234 int ret; in mt312_get_code_rate() local
237 ret = mt312_readreg(state, FEC_STATUS, &fec_status); in mt312_get_code_rate()
238 if (ret < 0) in mt312_get_code_rate()
239 return ret; in mt312_get_code_rate()
249 int ret; in mt312_initfe() local
253 ret = mt312_writereg(state, CONFIG, in mt312_initfe()
255 if (ret < 0) in mt312_initfe()
256 return ret; in mt312_initfe()
262 ret = mt312_reset(state, 1); in mt312_initfe()
263 if (ret < 0) in mt312_initfe()
264 return ret; in mt312_initfe()
272 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); in mt312_initfe()
273 if (ret < 0) in mt312_initfe()
274 return ret; in mt312_initfe()
280 ret = mt312_writereg(state, GPP_CTRL, 0x80); in mt312_initfe()
281 if (ret < 0) in mt312_initfe()
282 return ret; in mt312_initfe()
287 ret = mt312_write(state, HW_CTRL, buf, 2); in mt312_initfe()
288 if (ret < 0) in mt312_initfe()
289 return ret; in mt312_initfe()
292 ret = mt312_writereg(state, HW_CTRL, 0x00); in mt312_initfe()
293 if (ret < 0) in mt312_initfe()
294 return ret; in mt312_initfe()
296 ret = mt312_writereg(state, MPEG_CTRL, 0x00); in mt312_initfe()
297 if (ret < 0) in mt312_initfe()
298 return ret; in mt312_initfe()
309 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); in mt312_initfe()
310 if (ret < 0) in mt312_initfe()
311 return ret; in mt312_initfe()
313 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); in mt312_initfe()
314 if (ret < 0) in mt312_initfe()
315 return ret; in mt312_initfe()
327 ret = mt312_writereg(state, OP_CTRL, buf[0]); in mt312_initfe()
328 if (ret < 0) in mt312_initfe()
329 return ret; in mt312_initfe()
335 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); in mt312_initfe()
336 if (ret < 0) in mt312_initfe()
337 return ret; in mt312_initfe()
339 ret = mt312_writereg(state, CS_SW_LIM, 0x69); in mt312_initfe()
340 if (ret < 0) in mt312_initfe()
341 return ret; in mt312_initfe()
350 int ret; in mt312_send_master_cmd() local
356 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_master_cmd()
357 if (ret < 0) in mt312_send_master_cmd()
358 return ret; in mt312_send_master_cmd()
360 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); in mt312_send_master_cmd()
361 if (ret < 0) in mt312_send_master_cmd()
362 return ret; in mt312_send_master_cmd()
364 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_master_cmd()
367 if (ret < 0) in mt312_send_master_cmd()
368 return ret; in mt312_send_master_cmd()
375 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); in mt312_send_master_cmd()
376 if (ret < 0) in mt312_send_master_cmd()
377 return ret; in mt312_send_master_cmd()
388 int ret; in mt312_send_burst() local
394 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_burst()
395 if (ret < 0) in mt312_send_burst()
396 return ret; in mt312_send_burst()
398 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_burst()
400 if (ret < 0) in mt312_send_burst()
401 return ret; in mt312_send_burst()
411 int ret; in mt312_set_tone() local
417 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_set_tone()
418 if (ret < 0) in mt312_set_tone()
419 return ret; in mt312_set_tone()
421 ret = mt312_writereg(state, DISEQC_MODE, in mt312_set_tone()
423 if (ret < 0) in mt312_set_tone()
424 return ret; in mt312_set_tone()
448 int ret; in mt312_read_status() local
453 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); in mt312_read_status()
454 if (ret < 0) in mt312_read_status()
455 return ret; in mt312_read_status()
477 int ret; in mt312_read_ber() local
480 ret = mt312_read(state, RS_BERCNT_H, buf, 3); in mt312_read_ber()
481 if (ret < 0) in mt312_read_ber()
482 return ret; in mt312_read_ber()
493 int ret; in mt312_read_signal_strength() local
498 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); in mt312_read_signal_strength()
499 if (ret < 0) in mt312_read_signal_strength()
500 return ret; in mt312_read_signal_strength()
515 int ret; in mt312_read_snr() local
518 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); in mt312_read_snr()
519 if (ret < 0) in mt312_read_snr()
520 return ret; in mt312_read_snr()
530 int ret; in mt312_read_ucblocks() local
533 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); in mt312_read_ucblocks()
534 if (ret < 0) in mt312_read_ucblocks()
535 return ret; in mt312_read_ucblocks()
546 int ret; in mt312_set_frontend() local
582 ret = mt312_readreg(state, CONFIG, &config_val); in mt312_set_frontend()
583 if (ret < 0) in mt312_set_frontend()
584 return ret; in mt312_set_frontend()
590 ret = mt312_initfe(fe); in mt312_set_frontend()
591 if (ret < 0) in mt312_set_frontend()
592 return ret; in mt312_set_frontend()
598 ret = mt312_initfe(fe); in mt312_set_frontend()
599 if (ret < 0) in mt312_set_frontend()
600 return ret; in mt312_set_frontend()
638 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); in mt312_set_frontend()
639 if (ret < 0) in mt312_set_frontend()
640 return ret; in mt312_set_frontend()
651 int ret; in mt312_get_frontend() local
653 ret = mt312_get_inversion(state, &p->inversion); in mt312_get_frontend()
654 if (ret < 0) in mt312_get_frontend()
655 return ret; in mt312_get_frontend()
657 ret = mt312_get_symbol_rate(state, &p->symbol_rate); in mt312_get_frontend()
658 if (ret < 0) in mt312_get_frontend()
659 return ret; in mt312_get_frontend()
661 ret = mt312_get_code_rate(state, &p->fec_inner); in mt312_get_frontend()
662 if (ret < 0) in mt312_get_frontend()
663 return ret; in mt312_get_frontend()
673 int ret; in mt312_i2c_gate_ctrl() local
677 ret = mt312_readreg(state, GPP_CTRL, &val); in mt312_i2c_gate_ctrl()
678 if (ret < 0) in mt312_i2c_gate_ctrl()
691 ret = mt312_writereg(state, GPP_CTRL, val); in mt312_i2c_gate_ctrl()
694 return ret; in mt312_i2c_gate_ctrl()
700 int ret; in mt312_sleep() local
704 ret = mt312_reset(state, 1); in mt312_sleep()
705 if (ret < 0) in mt312_sleep()
706 return ret; in mt312_sleep()
710 ret = mt312_writereg(state, GPP_CTRL, 0x00); in mt312_sleep()
711 if (ret < 0) in mt312_sleep()
712 return ret; in mt312_sleep()
715 ret = mt312_writereg(state, HW_CTRL, 0x0d); in mt312_sleep()
716 if (ret < 0) in mt312_sleep()
717 return ret; in mt312_sleep()
720 ret = mt312_readreg(state, CONFIG, &config); in mt312_sleep()
721 if (ret < 0) in mt312_sleep()
722 return ret; in mt312_sleep()
725 ret = mt312_writereg(state, CONFIG, config & 0x7f); in mt312_sleep()
726 if (ret < 0) in mt312_sleep()
727 return ret; in mt312_sleep()