Lines Matching refs:state
128 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) in tda1004x_write_byteI() argument
136 msg.addr = state->config->demod_address; in tda1004x_write_byteI()
137 ret = i2c_transfer(state->i2c, &msg, 1); in tda1004x_write_byteI()
148 static int tda1004x_read_byte(struct tda1004x_state *state, int reg) in tda1004x_read_byte() argument
158 msg[0].addr = state->config->demod_address; in tda1004x_read_byte()
159 msg[1].addr = state->config->demod_address; in tda1004x_read_byte()
160 ret = i2c_transfer(state->i2c, msg, 2); in tda1004x_read_byte()
173 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) in tda1004x_write_mask() argument
180 val = tda1004x_read_byte(state, reg); in tda1004x_write_mask()
189 return tda1004x_write_byteI(state, reg, val); in tda1004x_write_mask()
192 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) in tda1004x_write_buf() argument
201 result = tda1004x_write_byteI(state, reg + i, buf[i]); in tda1004x_write_buf()
209 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) in tda1004x_enable_tuner_i2c() argument
214 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); in tda1004x_enable_tuner_i2c()
219 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) in tda1004x_disable_tuner_i2c() argument
223 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); in tda1004x_disable_tuner_i2c()
226 static int tda10045h_set_bandwidth(struct tda1004x_state *state, in tda10045h_set_bandwidth() argument
235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); in tda10045h_set_bandwidth()
239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); in tda10045h_set_bandwidth()
243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); in tda10045h_set_bandwidth()
250 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); in tda10045h_set_bandwidth()
255 static int tda10046h_set_bandwidth(struct tda1004x_state *state, in tda10046h_set_bandwidth() argument
267 if ((state->config->if_freq == TDA10046_FREQ_045) || in tda10046h_set_bandwidth()
268 (state->config->if_freq == TDA10046_FREQ_052)) in tda10046h_set_bandwidth()
275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, in tda10046h_set_bandwidth()
278 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M, in tda10046h_set_bandwidth()
280 if (state->config->if_freq == TDA10046_FREQ_045) { in tda10046h_set_bandwidth()
281 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); in tda10046h_set_bandwidth()
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab); in tda10046h_set_bandwidth()
288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, in tda10046h_set_bandwidth()
291 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M, in tda10046h_set_bandwidth()
293 if (state->config->if_freq == TDA10046_FREQ_045) { in tda10046h_set_bandwidth()
294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); in tda10046h_set_bandwidth()
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); in tda10046h_set_bandwidth()
301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, in tda10046h_set_bandwidth()
304 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M, in tda10046h_set_bandwidth()
306 if (state->config->if_freq == TDA10046_FREQ_045) { in tda10046h_set_bandwidth()
307 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); in tda10046h_set_bandwidth()
308 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55); in tda10046h_set_bandwidth()
319 static int tda1004x_do_upload(struct tda1004x_state *state, in tda1004x_do_upload() argument
329 tda1004x_write_byteI(state, dspCodeCounterReg, 0); in tda1004x_do_upload()
330 fw_msg.addr = state->config->demod_address; in tda1004x_do_upload()
332 i2c_lock_adapter(state->i2c); in tda1004x_do_upload()
343 if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) { in tda1004x_do_upload()
345 i2c_unlock_adapter(state->i2c); in tda1004x_do_upload()
352 i2c_unlock_adapter(state->i2c); in tda1004x_do_upload()
360 static int tda1004x_check_upload_ok(struct tda1004x_state *state) in tda1004x_check_upload_ok() argument
365 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { in tda1004x_check_upload_ok()
367 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { in tda1004x_check_upload_ok()
378 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP in tda1004x_check_upload_ok()
379 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); in tda1004x_check_upload_ok()
381 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); in tda1004x_check_upload_ok()
382 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); in tda1004x_check_upload_ok()
393 struct tda1004x_state* state = fe->demodulator_priv; in tda10045_fwupload() local
398 if (tda1004x_check_upload_ok(state) == 0) in tda10045_fwupload()
403 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); in tda10045_fwupload()
410 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); in tda10045_fwupload()
411 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda10045_fwupload()
412 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda10045_fwupload()
416 tda10045h_set_bandwidth(state, 8000000); in tda10045_fwupload()
418 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); in tda10045_fwupload()
428 return tda1004x_check_upload_ok(state); in tda10045_fwupload()
433 struct tda1004x_state* state = fe->demodulator_priv; in tda10046_init_plls() local
436 if ((state->config->if_freq == TDA10046_FREQ_045) || in tda10046_init_plls()
437 (state->config->if_freq == TDA10046_FREQ_052)) in tda10046_init_plls()
442 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); in tda10046_init_plls()
445 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8 in tda10046_init_plls()
448 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3 in tda10046_init_plls()
450 if (state->config->xtal_freq == TDA10046_XTAL_4M ) { in tda10046_init_plls()
452 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 in tda10046_init_plls()
455 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 in tda10046_init_plls()
458 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67); in tda10046_init_plls()
460 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72); in tda10046_init_plls()
462 switch (state->config->if_freq) { in tda10046_init_plls()
464 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); in tda10046_init_plls()
465 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); in tda10046_init_plls()
468 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); in tda10046_init_plls()
469 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7); in tda10046_init_plls()
472 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); in tda10046_init_plls()
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59); in tda10046_init_plls()
476 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); in tda10046_init_plls()
477 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); in tda10046_init_plls()
480 tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */ in tda10046_init_plls()
487 struct tda1004x_state* state = fe->demodulator_priv; in tda10046_fwupload() local
492 if (state->config->xtal_freq == TDA10046_XTAL_4M) { in tda10046_fwupload()
498 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); in tda10046_fwupload()
500 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); in tda10046_fwupload()
502 if (state->config->gpio_config != TDA10046_GPTRI) { in tda10046_fwupload()
503 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33); in tda10046_fwupload()
504 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f); in tda10046_fwupload()
511 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0); in tda10046_fwupload()
514 if (tda1004x_check_upload_ok(state) == 0) in tda10046_fwupload()
530 tda1004x_write_byteI(state, TDA1004X_CONFC4, 4); in tda10046_fwupload()
532 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); in tda10046_fwupload()
535 if (tda1004x_check_upload_ok(state) == 0) in tda10046_fwupload()
540 if (state->config->request_firmware != NULL) { in tda10046_fwupload()
543 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); in tda10046_fwupload()
546 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); in tda10046_fwupload()
559 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST in tda10046_fwupload()
560 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); in tda10046_fwupload()
562 return tda1004x_check_upload_ok(state); in tda10046_fwupload()
607 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_write() local
612 return tda1004x_write_byteI(state, buf[0], buf[1]); in tda1004x_write()
617 struct tda1004x_state* state = fe->demodulator_priv; in tda10045_init() local
626 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC in tda10045_init()
629 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10045_init()
630 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream in tda10045_init()
631 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal in tda10045_init()
632 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer in tda10045_init()
633 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset in tda10045_init()
634 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset in tda10045_init()
635 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface in tda10045_init()
636 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface in tda10045_init()
637 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits in tda10045_init()
638 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity in tda10045_init()
639 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); in tda10045_init()
641 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); in tda10045_init()
648 struct tda1004x_state* state = fe->demodulator_priv; in tda10046_init() local
657 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10046_init()
658 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream in tda10046_init()
659 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer in tda10046_init()
661 switch (state->config->agc_config) { in tda10046_init()
663 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup in tda10046_init()
664 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
667 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup in tda10046_init()
668 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
671 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup in tda10046_init()
672 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities in tda10046_init()
675 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup in tda10046_init()
676 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold in tda10046_init()
677 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize in tda10046_init()
678 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
681 if (state->config->ts_mode == 0) { in tda10046_init()
682 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40); in tda10046_init()
683 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); in tda10046_init()
685 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80); in tda10046_init()
686 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10, in tda10046_init()
687 state->config->invert_oclk << 4); in tda10046_init()
689 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38); in tda10046_init()
690 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on in tda10046_init()
691 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } in tda10046_init()
692 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values in tda10046_init()
693 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } in tda10046_init()
694 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } in tda10046_init()
695 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1 in tda10046_init()
696 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits in tda10046_init()
697 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config in tda10046_init()
698 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config in tda10046_init()
707 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_set_fe() local
713 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { in tda1004x_set_fe()
715 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); in tda1004x_set_fe()
716 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); in tda1004x_set_fe()
717 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); in tda1004x_set_fe()
720 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); in tda1004x_set_fe()
732 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { in tda1004x_set_fe()
743 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto in tda1004x_set_fe()
744 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */ in tda1004x_set_fe()
745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits in tda1004x_set_fe()
746 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits in tda1004x_set_fe()
748 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto in tda1004x_set_fe()
754 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); in tda1004x_set_fe()
760 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); in tda1004x_set_fe()
765 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); in tda1004x_set_fe()
769 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); in tda1004x_set_fe()
773 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); in tda1004x_set_fe()
783 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); in tda1004x_set_fe()
787 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); in tda1004x_set_fe()
791 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); in tda1004x_set_fe()
795 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); in tda1004x_set_fe()
804 switch (state->demod_type) { in tda1004x_set_fe()
806 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz); in tda1004x_set_fe()
810 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz); in tda1004x_set_fe()
816 if (state->config->invert) in tda1004x_set_fe()
820 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); in tda1004x_set_fe()
824 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); in tda1004x_set_fe()
834 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
835 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
839 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
840 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); in tda1004x_set_fe()
844 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
845 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); in tda1004x_set_fe()
849 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
850 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); in tda1004x_set_fe()
854 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); in tda1004x_set_fe()
855 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
865 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
866 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); in tda1004x_set_fe()
870 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
871 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); in tda1004x_set_fe()
875 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); in tda1004x_set_fe()
876 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); in tda1004x_set_fe()
884 switch (state->demod_type) { in tda1004x_set_fe()
886 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda1004x_set_fe()
887 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda1004x_set_fe()
891 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); in tda1004x_set_fe()
893 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1); in tda1004x_set_fe()
905 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_get_fe() local
910 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); in tda1004x_get_fe()
920 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) in tda1004x_get_fe()
922 if (state->config->invert) in tda1004x_get_fe()
926 switch (state->demod_type) { in tda1004x_get_fe()
928 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { in tda1004x_get_fe()
941 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { in tda1004x_get_fe()
960 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); in tda1004x_get_fe()
962 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); in tda1004x_get_fe()
965 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { in tda1004x_get_fe()
979 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) in tda1004x_get_fe()
983 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { in tda1004x_get_fe()
999 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { in tda1004x_get_fe()
1019 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_status() local
1027 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); in tda1004x_read_status()
1044 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); in tda1004x_read_status()
1047 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); in tda1004x_read_status()
1052 tda1004x_read_byte(state, TDA1004X_CBER_RESET); in tda1004x_read_status()
1062 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); in tda1004x_read_status()
1065 status = tda1004x_read_byte(state, TDA1004X_VBER_MID); in tda1004x_read_status()
1069 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); in tda1004x_read_status()
1074 tda1004x_read_byte(state, TDA1004X_CVBER_LUT); in tda1004x_read_status()
1089 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_signal_strength() local
1096 switch (state->demod_type) { in tda1004x_read_signal_strength()
1107 tmp = tda1004x_read_byte(state, reg); in tda1004x_read_signal_strength()
1118 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_snr() local
1124 tmp = tda1004x_read_byte(state, TDA1004X_SNR); in tda1004x_read_snr()
1136 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_ucblocks() local
1145 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); in tda1004x_read_ucblocks()
1150 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1151 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1152 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1154 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); in tda1004x_read_ucblocks()
1173 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_ber() local
1179 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); in tda1004x_read_ber()
1183 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); in tda1004x_read_ber()
1188 tda1004x_read_byte(state, TDA1004X_CBER_RESET); in tda1004x_read_ber()
1196 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_sleep() local
1199 switch (state->demod_type) { in tda1004x_sleep()
1201 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); in tda1004x_sleep()
1206 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff); in tda1004x_sleep()
1208 gpio_conf = state->config->gpio_config; in tda1004x_sleep()
1210 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, in tda1004x_sleep()
1213 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0); in tda1004x_sleep()
1214 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); in tda1004x_sleep()
1223 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_i2c_gate_ctrl() local
1226 return tda1004x_enable_tuner_i2c(state); in tda1004x_i2c_gate_ctrl()
1228 return tda1004x_disable_tuner_i2c(state); in tda1004x_i2c_gate_ctrl()
1243 struct tda1004x_state *state = fe->demodulator_priv; in tda1004x_release() local
1244 kfree(state); in tda1004x_release()
1282 struct tda1004x_state *state; in tda10045_attach() local
1286 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); in tda10045_attach()
1287 if (!state) { in tda10045_attach()
1293 state->config = config; in tda10045_attach()
1294 state->i2c = i2c; in tda10045_attach()
1295 state->demod_type = TDA1004X_DEMOD_TDA10045; in tda10045_attach()
1298 id = tda1004x_read_byte(state, TDA1004X_CHIPID); in tda10045_attach()
1301 kfree(state); in tda10045_attach()
1307 kfree(state); in tda10045_attach()
1312 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); in tda10045_attach()
1313 state->frontend.demodulator_priv = state; in tda10045_attach()
1314 return &state->frontend; in tda10045_attach()
1352 struct tda1004x_state *state; in tda10046_attach() local
1356 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); in tda10046_attach()
1357 if (!state) { in tda10046_attach()
1363 state->config = config; in tda10046_attach()
1364 state->i2c = i2c; in tda10046_attach()
1365 state->demod_type = TDA1004X_DEMOD_TDA10046; in tda10046_attach()
1368 id = tda1004x_read_byte(state, TDA1004X_CHIPID); in tda10046_attach()
1371 kfree(state); in tda10046_attach()
1376 kfree(state); in tda10046_attach()
1381 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); in tda10046_attach()
1382 state->frontend.demodulator_priv = state; in tda10046_attach()
1383 return &state->frontend; in tda10046_attach()