59 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)  in ves1820_writereg()  function
105 	ves1820_writereg(state, 0x00, reg0 & 0xfe);  in ves1820_setup_reg0()
106 	ves1820_writereg(state, 0x00, reg0 | 0x01);  in ves1820_setup_reg0()
180 	ves1820_writereg(state, 0x03, NDEC);  in ves1820_set_symbolrate()
181 	ves1820_writereg(state, 0x0a, BDR & 0xff);  in ves1820_set_symbolrate()
182 	ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);  in ves1820_set_symbolrate()
183 	ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);  in ves1820_set_symbolrate()
185 	ves1820_writereg(state, 0x0d, BDRI);  in ves1820_set_symbolrate()
186 	ves1820_writereg(state, 0x0e, SFIL);  in ves1820_set_symbolrate()
196 	ves1820_writereg(state, 0, 0);  in ves1820_init()
199 		ves1820_writereg(state, i, ves1820_inittab[i]);  in ves1820_init()
201 		ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);  in ves1820_init()
203 	ves1820_writereg(state, 0x34, state->pwm);  in ves1820_init()
228 	ves1820_writereg(state, 0x34, state->pwm);  in ves1820_set_parameters()
230 	ves1820_writereg(state, 0x01, reg0x01[real_qam]);  in ves1820_set_parameters()
231 	ves1820_writereg(state, 0x05, reg0x05[real_qam]);  in ves1820_set_parameters()
232 	ves1820_writereg(state, 0x08, reg0x08[real_qam]);  in ves1820_set_parameters()
233 	ves1820_writereg(state, 0x09, reg0x09[real_qam]);  in ves1820_set_parameters()
236 	ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));  in ves1820_set_parameters()
307 	ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);  in ves1820_read_ucblocks()
308 	ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);  in ves1820_read_ucblocks()
349 	ves1820_writereg(state, 0x1b, 0x02);	/* pdown ADC */  in ves1820_sleep()
350 	ves1820_writereg(state, 0x00, 0x80);	/* standby */  in ves1820_sleep()