862 	for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {  in find_and_set_predefined_video_timings()
924 		const struct v4l2_bt_timings *bt)  in configure_custom_video_timings()  argument
927 	u32 width = htotal(bt);  in configure_custom_video_timings()
928 	u32 height = vtotal(bt);  in configure_custom_video_timings()
929 	u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;  in configure_custom_video_timings()
930 	u16 cp_start_eav = width - bt->hfrontporch;  in configure_custom_video_timings()
931 	u16 cp_start_vbi = height - bt->vfrontporch;  in configure_custom_video_timings()
932 	u16 cp_end_vbi = bt->vsync + bt->vbackporch;  in configure_custom_video_timings()
933 	u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?  in configure_custom_video_timings()
934 		((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;  in configure_custom_video_timings()
1078 		if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {  in set_rgb_quantization_range()
1289 	for (i = 0; adv76xx_timings[i].bt.height; i++) {  in stdi2dv_timings()
1290 		if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)  in stdi2dv_timings()
1292 		if (adv76xx_timings[i].bt.vsync != stdi->lcvs)  in stdi2dv_timings()
1295 		pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);  in stdi2dv_timings()
1297 		if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&  in stdi2dv_timings()
1298 		    (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {  in stdi2dv_timings()
1404 	cap->bt.max_width = 1920;  in adv76xx_dv_timings_cap()
1405 	cap->bt.max_height = 1200;  in adv76xx_dv_timings_cap()
1406 	cap->bt.min_pixelclock = 25000000;  in adv76xx_dv_timings_cap()
1413 		cap->bt.max_pixelclock = 225000000;  in adv76xx_dv_timings_cap()
1418 		cap->bt.max_pixelclock = 170000000;  in adv76xx_dv_timings_cap()
1422 	cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |  in adv76xx_dv_timings_cap()
1424 	cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |  in adv76xx_dv_timings_cap()
1436 	for (i = 0; adv76xx_timings[i].bt.width; i++) {  in adv76xx_fill_optional_dv_timings_fields()
1482 	struct v4l2_bt_timings *bt = &timings->bt;  in adv76xx_query_dv_timings()  local
1501 	bt->interlaced = stdi.interlaced ?  in adv76xx_query_dv_timings()
1508 		bt->width = hdmi_read16(sd, 0x07, 0xfff);  in adv76xx_query_dv_timings()
1509 		bt->height = hdmi_read16(sd, 0x09, 0xfff);  in adv76xx_query_dv_timings()
1510 		bt->pixelclock = info->read_hdmi_pixelclock(sd);  in adv76xx_query_dv_timings()
1511 		bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);  in adv76xx_query_dv_timings()
1512 		bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);  in adv76xx_query_dv_timings()
1513 		bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);  in adv76xx_query_dv_timings()
1514 		bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;  in adv76xx_query_dv_timings()
1515 		bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;  in adv76xx_query_dv_timings()
1516 		bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;  in adv76xx_query_dv_timings()
1517 		bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |  in adv76xx_query_dv_timings()
1519 		if (bt->interlaced == V4L2_DV_INTERLACED) {  in adv76xx_query_dv_timings()
1520 			bt->height += hdmi_read16(sd, 0x0b, 0xfff);  in adv76xx_query_dv_timings()
1521 			bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;  in adv76xx_query_dv_timings()
1522 			bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;  in adv76xx_query_dv_timings()
1523 			bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;  in adv76xx_query_dv_timings()
1574 	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||  in adv76xx_query_dv_timings()
1575 			(is_digital_input(sd) && bt->pixelclock > 225000000)) {  in adv76xx_query_dv_timings()
1577 				__func__, (u32)bt->pixelclock);  in adv76xx_query_dv_timings()
1592 	struct v4l2_bt_timings *bt;  in adv76xx_s_dv_timings()  local
1603 	bt = &timings->bt;  in adv76xx_s_dv_timings()
1605 	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||  in adv76xx_s_dv_timings()
1606 			(is_digital_input(sd) && bt->pixelclock > 225000000)) {  in adv76xx_s_dv_timings()
1608 				__func__, (u32)bt->pixelclock);  in adv76xx_s_dv_timings()
1616 	cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);  in adv76xx_s_dv_timings()
1623 		configure_custom_video_timings(sd, bt);  in adv76xx_s_dv_timings()
1755 	format->width = state->timings.bt.width;  in adv76xx_fill_format()
1756 	format->height = state->timings.bt.height;  in adv76xx_fill_format()
1760 	if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)  in adv76xx_fill_format()
1761 		format->colorspace = (state->timings.bt.height <= 576) ?  in adv76xx_fill_format()