252 	u16 reg_val =   MT9M032_FORMATTER2_DOUT_EN  in update_formatter2()  local
257 		reg_val |= MT9M032_FORMATTER2_PIXCLK_EN;   /* pixclock enable */  in update_formatter2()
259 	return mt9m032_write(client, MT9M032_FORMATTER2, reg_val);  in update_formatter2()
283 	u16 reg_val;  in mt9m032_setup_pll()  local
307 		reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0)  in mt9m032_setup_pll()
309 		ret = mt9m032_write(client, MT9M032_FORMATTER1, reg_val);  in mt9m032_setup_pll()
598 	int reg_val = (vflip << MT9M032_READ_MODE2_VFLIP_SHIFT)  in update_read_mode2()  local
603 	return mt9m032_write(client, MT9M032_READ_MODE2, reg_val);  in update_read_mode2()
612 	u16 reg_val;  in mt9m032_set_gain()  local
627 	reg_val = ((digital_gain_val & MT9M032_GAIN_DIGITAL_MASK)  in mt9m032_set_gain()
632 	return mt9m032_write(client, MT9M032_GAIN_ALL, reg_val);  in mt9m032_set_gain()