27 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)  in cx18_memset_io()  argument
30 	u16 val2 = val | (val << 8);  in cx18_memset_io()
35 		cx18_writeb(cx, (u8) val, dst);  in cx18_memset_io()
55 		cx18_writeb(cx, (u8) val, dst);  in cx18_memset_io()
58 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)  in cx18_sw1_irq_enable()  argument
60 	cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);  in cx18_sw1_irq_enable()
61 	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;  in cx18_sw1_irq_enable()
65 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)  in cx18_sw1_irq_disable()  argument
67 	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;  in cx18_sw1_irq_disable()
71 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)  in cx18_sw2_irq_enable()  argument
73 	cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);  in cx18_sw2_irq_enable()
74 	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;  in cx18_sw2_irq_enable()
78 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)  in cx18_sw2_irq_disable()  argument
80 	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;  in cx18_sw2_irq_disable()
84 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)  in cx18_sw2_irq_disable_cpu()  argument
88 	cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);  in cx18_sw2_irq_disable_cpu()
93 	u32 val;  in cx18_setup_page()  local
94 	val = cx18_read_reg(cx, 0xD000F8);  in cx18_setup_page()
95 	val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);  in cx18_setup_page()
96 	cx18_write_reg(cx, val, 0xD000F8);  in cx18_setup_page()