Lines Matching refs:smi_write
38 smi_write(MUX_MODE_CTRL, port_mux); in smi_hw_init()
44 smi_write(VIDEO_CTRL_STATUS_A, port_ctrl); in smi_hw_init()
48 smi_write(MPEG2_CTRL_A, port_ctrl); in smi_hw_init()
52 smi_write(VIDEO_CTRL_STATUS_B, port_ctrl); in smi_hw_init()
56 smi_write(MPEG2_CTRL_B, port_ctrl); in smi_hw_init()
59 smi_write(MSI_INT_ENA_CLR, ALL_INT); in smi_hw_init()
61 smi_write(MSI_INT_STATUS_CLR, int_stat); in smi_hw_init()
80 smi_write(sw_ctl, dwCtrl); in smi_i2c_cfg()
84 smi_write(sw_ctl, dwCtrl); in smi_i2c_cfg()
271 smi_write(MSI_INT_ENA_CLR, in smi_port_disableInterrupt()
279 smi_write(MSI_INT_ENA_SET, in smi_port_enableInterrupt()
287 smi_write(MSI_INT_STATUS_CLR, in smi_port_clearInterrupt()
355 smi_write(port->DMA_MANAGEMENT, dmaManagement); in smi_dma_xfer()
791 smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow); in smi_config_DMA()
792 smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi); in smi_config_DMA()
793 smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg); in smi_config_DMA()
806 smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow); in smi_config_DMA()
807 smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi); in smi_config_DMA()
808 smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg); in smi_config_DMA()
824 smi_write(port->DMA_MANAGEMENT, dmaManagement); in smi_start_feed()
1031 smi_write(MSI_INT_ENA_CLR, ALL_INT); in smi_remove()