214 static struct viu_reg reg_val;  variable
442 	reg_val.field_base_addr = videobuf_to_dma_contig(&buf->vb);  in buffer_activate()
445 		buf, buf->vb.i, (unsigned long)reg_val.field_base_addr);  in buffer_activate()
448 	reg_val.status_cfg = 0;  in buffer_activate()
452 		reg_val.status_cfg &= ~MODE_32BIT;  in buffer_activate()
453 		reg_val.dma_inc = buf->vb.width * 2;  in buffer_activate()
456 		reg_val.status_cfg |= MODE_32BIT;  in buffer_activate()
457 		reg_val.dma_inc = buf->vb.width * 4;  in buffer_activate()
466 	reg_val.picture_count = (buf->vb.height / 2) << 16 |  in buffer_activate()
469 	reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN;  in buffer_activate()
476 		reg_val.dma_inc = 0;  in buffer_activate()
478 	out_be32(&vr->dma_inc, reg_val.dma_inc);  in buffer_activate()
479 	out_be32(&vr->picture_count, reg_val.picture_count);  in buffer_activate()
480 	out_be32(&vr->field_base_addr, reg_val.field_base_addr);  in buffer_activate()
758 	out_be32(&vr->field_base_addr, reg_val.field_base_addr);  in viu_activate_overlay()
759 	out_be32(&vr->dma_inc, reg_val.dma_inc);  in viu_activate_overlay()
760 	out_be32(&vr->picture_count, reg_val.picture_count);  in viu_activate_overlay()
770 	reg_val.status_cfg = 0;  in viu_setup_preview()
773 	reg_val.picture_count = (fh->win.w.height / 2) << 16 |  in viu_setup_preview()
780 		reg_val.status_cfg &= ~MODE_32BIT;  in viu_setup_preview()
781 		reg_val.dma_inc = fh->win.w.width * 2;  in viu_setup_preview()
784 		reg_val.status_cfg |= MODE_32BIT;  in viu_setup_preview()
785 		reg_val.dma_inc = fh->win.w.width * 4;  in viu_setup_preview()
795 		reg_val.dma_inc = 0;  in viu_setup_preview()
797 	reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN;  in viu_setup_preview()
800 	reg_val.field_base_addr = (u32)dev->ovbuf.base;  in viu_setup_preview()
1104 			u32 addr = reg_val.field_base_addr;  in viu_overlay_intr()
1108 				addr += reg_val.dma_inc;  in viu_overlay_intr()
1111 			out_be32(&vr->dma_inc, reg_val.dma_inc);  in viu_overlay_intr()
1115 				 reg_val.status_cfg);  in viu_overlay_intr()
1120 				 reg_val.status_cfg);  in viu_overlay_intr()
1159 			u32 addr = reg_val.field_base_addr;  in viu_capture_intr()
1162 				addr += reg_val.dma_inc;  in viu_capture_intr()
1167 			out_be32(&vr->dma_inc, reg_val.dma_inc);  in viu_capture_intr()
1171 				 reg_val.status_cfg);  in viu_capture_intr()