27 static inline void vp_write(struct mxr_device *mdev, u32 reg_id, u32 val)  in vp_write()  argument
29 	writel(val, mdev->res.vp_regs + reg_id);  in vp_write()
33 	u32 val, u32 mask)  in vp_write_mask()  argument
37 	val = (val & mask) | (old & ~mask);  in vp_write_mask()
38 	writel(val, mdev->res.vp_regs + reg_id);  in vp_write_mask()
46 static inline void mxr_write(struct mxr_device *mdev, u32 reg_id, u32 val)  in mxr_write()  argument
48 	writel(val, mdev->res.mxr_regs + reg_id);  in mxr_write()
52 	u32 val, u32 mask)  in mxr_write_mask()  argument
56 	val = (val & mask) | (old & ~mask);  in mxr_write_mask()
57 	writel(val, mdev->res.mxr_regs + reg_id);  in mxr_write_mask()
87 	u32 val; /* value stored to register */  in mxr_reg_reset()  local
105 	val  = MXR_LAYER_CFG_GRP0_VAL(1);  in mxr_reg_reset()
106 	val |= MXR_LAYER_CFG_VP_VAL(2);  in mxr_reg_reset()
107 	val |= MXR_LAYER_CFG_GRP1_VAL(3);  in mxr_reg_reset()
108 	mxr_write(mdev, MXR_LAYER_CFG, val);  in mxr_reg_reset()
117 	val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */  in mxr_reg_reset()
118 	val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */  in mxr_reg_reset()
119 	val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */  in mxr_reg_reset()
122 	mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);  in mxr_reg_reset()
123 	mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);  in mxr_reg_reset()
139 	u32 val;  in mxr_reg_graph_format()  local
151 	val  = MXR_GRP_WH_WIDTH(geo->src.width);  in mxr_reg_graph_format()
152 	val |= MXR_GRP_WH_HEIGHT(geo->src.height);  in mxr_reg_graph_format()
153 	val |= MXR_GRP_WH_H_SCALE(geo->x_ratio);  in mxr_reg_graph_format()
154 	val |= MXR_GRP_WH_V_SCALE(geo->y_ratio);  in mxr_reg_graph_format()
155 	mxr_write(mdev, MXR_GRAPHIC_WH(idx), val);  in mxr_reg_graph_format()
158 	val  = MXR_GRP_SXY_SX(geo->src.x_offset);  in mxr_reg_graph_format()
159 	val |= MXR_GRP_SXY_SY(geo->src.y_offset);  in mxr_reg_graph_format()
160 	mxr_write(mdev, MXR_GRAPHIC_SXY(idx), val);  in mxr_reg_graph_format()
163 	val  = MXR_GRP_DXY_DX(geo->dst.x_offset);  in mxr_reg_graph_format()
164 	val |= MXR_GRP_DXY_DY(geo->dst.y_offset);  in mxr_reg_graph_format()
165 	mxr_write(mdev, MXR_GRAPHIC_DXY(idx), val);  in mxr_reg_graph_format()
216 	u32 val = addr ? ~0 : 0;  in mxr_reg_graph_buffer()  local
223 		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);  in mxr_reg_graph_buffer()
225 		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);  in mxr_reg_graph_buffer()
235 	u32 val = luma_addr[0] ? ~0 : 0;  in mxr_reg_vp_buffer()  local
241 	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VP_ENABLE);  in mxr_reg_vp_buffer()
242 	vp_write_mask(mdev, VP_ENABLE, val, VP_ENABLE_ON);  in mxr_reg_vp_buffer()
291 	u32 i, val;  in mxr_irq_handler()  local
294 	val = mxr_read(mdev, MXR_INT_STATUS);  in mxr_irq_handler()
297 	if (val & MXR_INT_STATUS_VSYNC) {  in mxr_irq_handler()
304 		val &= ~MXR_INT_STATUS_VSYNC;  in mxr_irq_handler()
305 		val |= MXR_INT_CLEAR_VSYNC;  in mxr_irq_handler()
309 	mxr_write(mdev, MXR_INT_STATUS, val);  in mxr_irq_handler()
313 	if (~val & MXR_INT_CLEAR_VSYNC)  in mxr_irq_handler()
325 	u32 val;  in mxr_reg_s_output()  local
327 	val = cookie == 0 ? MXR_CFG_DST_SDO : MXR_CFG_DST_HDMI;  in mxr_reg_s_output()
328 	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_DST_MASK);  in mxr_reg_s_output()
378 	u32 val = 0;  in mxr_reg_set_mbus_fmt()  local
386 		val |= MXR_CFG_OUT_YUV444;  in mxr_reg_set_mbus_fmt()
388 		val |= MXR_CFG_OUT_RGB888;  in mxr_reg_set_mbus_fmt()
392 		val |= MXR_CFG_SCAN_INTERLACE;  in mxr_reg_set_mbus_fmt()
394 		val |= MXR_CFG_SCAN_PROGRASSIVE;  in mxr_reg_set_mbus_fmt()
398 		val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;  in mxr_reg_set_mbus_fmt()
400 		val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;  in mxr_reg_set_mbus_fmt()
402 		val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;  in mxr_reg_set_mbus_fmt()
404 		val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;  in mxr_reg_set_mbus_fmt()
408 	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |  in mxr_reg_set_mbus_fmt()
411 	val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;  in mxr_reg_set_mbus_fmt()
412 	vp_write_mask(mdev, VP_MODE, val,  in mxr_reg_set_mbus_fmt()
464 		u32 val = (data[0] << 24) |  (data[1] << 16) |  in mxr_reg_vp_filter_set()  local
466 		vp_write(mdev, reg_id, val);  in mxr_reg_vp_filter_set()