Lines Matching refs:nvt
43 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) in nvt_cr_write() argument
45 outb(reg, nvt->cr_efir); in nvt_cr_write()
46 outb(val, nvt->cr_efdr); in nvt_cr_write()
50 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) in nvt_cr_read() argument
52 outb(reg, nvt->cr_efir); in nvt_cr_read()
53 return inb(nvt->cr_efdr); in nvt_cr_read()
57 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) in nvt_set_reg_bit() argument
59 u8 tmp = nvt_cr_read(nvt, reg) | val; in nvt_set_reg_bit()
60 nvt_cr_write(nvt, tmp, reg); in nvt_set_reg_bit()
64 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) in nvt_clear_reg_bit() argument
66 u8 tmp = nvt_cr_read(nvt, reg) & ~val; in nvt_clear_reg_bit()
67 nvt_cr_write(nvt, tmp, reg); in nvt_clear_reg_bit()
71 static inline void nvt_efm_enable(struct nvt_dev *nvt) in nvt_efm_enable() argument
74 outb(EFER_EFM_ENABLE, nvt->cr_efir); in nvt_efm_enable()
75 outb(EFER_EFM_ENABLE, nvt->cr_efir); in nvt_efm_enable()
79 static inline void nvt_efm_disable(struct nvt_dev *nvt) in nvt_efm_disable() argument
81 outb(EFER_EFM_DISABLE, nvt->cr_efir); in nvt_efm_disable()
89 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) in nvt_select_logical_dev() argument
91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir); in nvt_select_logical_dev()
92 outb(ldev, nvt->cr_efdr); in nvt_select_logical_dev()
96 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) in nvt_cir_reg_write() argument
98 outb(val, nvt->cir_addr + offset); in nvt_cir_reg_write()
102 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) in nvt_cir_reg_read() argument
106 val = inb(nvt->cir_addr + offset); in nvt_cir_reg_read()
112 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, in nvt_cir_wake_reg_write() argument
115 outb(val, nvt->cir_wake_addr + offset); in nvt_cir_wake_reg_write()
119 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) in nvt_cir_wake_reg_read() argument
123 val = inb(nvt->cir_wake_addr + offset); in nvt_cir_wake_reg_read()
129 static void cir_dump_regs(struct nvt_dev *nvt) in cir_dump_regs() argument
131 nvt_efm_enable(nvt); in cir_dump_regs()
132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); in cir_dump_regs()
136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); in cir_dump_regs()
138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | in cir_dump_regs()
139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); in cir_dump_regs()
141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); in cir_dump_regs()
143 nvt_efm_disable(nvt); in cir_dump_regs()
146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); in cir_dump_regs()
147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); in cir_dump_regs()
148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); in cir_dump_regs()
149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); in cir_dump_regs()
150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); in cir_dump_regs()
151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); in cir_dump_regs()
152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); in cir_dump_regs()
153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); in cir_dump_regs()
154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); in cir_dump_regs()
155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); in cir_dump_regs()
156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); in cir_dump_regs()
157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); in cir_dump_regs()
158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); in cir_dump_regs()
159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); in cir_dump_regs()
160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); in cir_dump_regs()
161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); in cir_dump_regs()
165 static void cir_wake_dump_regs(struct nvt_dev *nvt) in cir_wake_dump_regs() argument
169 nvt_efm_enable(nvt); in cir_wake_dump_regs()
170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); in cir_wake_dump_regs()
175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); in cir_wake_dump_regs()
177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | in cir_wake_dump_regs()
178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); in cir_wake_dump_regs()
180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); in cir_wake_dump_regs()
182 nvt_efm_disable(nvt); in cir_wake_dump_regs()
186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); in cir_wake_dump_regs()
188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); in cir_wake_dump_regs()
190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); in cir_wake_dump_regs()
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); in cir_wake_dump_regs()
194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); in cir_wake_dump_regs()
196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); in cir_wake_dump_regs()
198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); in cir_wake_dump_regs()
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); in cir_wake_dump_regs()
202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); in cir_wake_dump_regs()
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); in cir_wake_dump_regs()
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); in cir_wake_dump_regs()
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); in cir_wake_dump_regs()
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); in cir_wake_dump_regs()
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); in cir_wake_dump_regs()
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); in cir_wake_dump_regs()
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); in cir_wake_dump_regs()
218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); in cir_wake_dump_regs()
223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); in cir_wake_dump_regs()
228 static int nvt_hw_detect(struct nvt_dev *nvt) in nvt_hw_detect() argument
235 nvt_efm_enable(nvt); in nvt_hw_detect()
238 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); in nvt_hw_detect()
240 nvt->cr_efir = CR_EFIR2; in nvt_hw_detect()
241 nvt->cr_efdr = CR_EFDR2; in nvt_hw_detect()
242 nvt_efm_enable(nvt); in nvt_hw_detect()
243 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); in nvt_hw_detect()
246 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); in nvt_hw_detect()
280 nvt_efm_disable(nvt); in nvt_hw_detect()
282 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_hw_detect()
283 nvt->chip_major = chip_major; in nvt_hw_detect()
284 nvt->chip_minor = chip_minor; in nvt_hw_detect()
285 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_hw_detect()
290 static void nvt_cir_ldev_init(struct nvt_dev *nvt) in nvt_cir_ldev_init() argument
294 if (nvt->chip_major == CHIP_ID_HIGH_667) { in nvt_cir_ldev_init()
305 val = nvt_cr_read(nvt, psreg); in nvt_cir_ldev_init()
308 nvt_cr_write(nvt, val, psreg); in nvt_cir_ldev_init()
311 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); in nvt_cir_ldev_init()
312 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_cir_ldev_init()
314 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI); in nvt_cir_ldev_init()
315 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO); in nvt_cir_ldev_init()
317 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); in nvt_cir_ldev_init()
320 nvt->cir_addr, nvt->cir_irq); in nvt_cir_ldev_init()
323 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) in nvt_cir_wake_ldev_init() argument
326 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); in nvt_cir_wake_ldev_init()
327 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_cir_wake_ldev_init()
330 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); in nvt_cir_wake_ldev_init()
333 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); in nvt_cir_wake_ldev_init()
336 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); in nvt_cir_wake_ldev_init()
337 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_cir_wake_ldev_init()
339 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI); in nvt_cir_wake_ldev_init()
340 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO); in nvt_cir_wake_ldev_init()
342 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC); in nvt_cir_wake_ldev_init()
345 nvt->cir_wake_addr, nvt->cir_wake_irq); in nvt_cir_wake_ldev_init()
349 static void nvt_clear_cir_fifo(struct nvt_dev *nvt) in nvt_clear_cir_fifo() argument
353 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); in nvt_clear_cir_fifo()
354 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); in nvt_clear_cir_fifo()
358 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) in nvt_clear_cir_wake_fifo() argument
362 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); in nvt_clear_cir_wake_fifo()
363 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, in nvt_clear_cir_wake_fifo()
368 static void nvt_clear_tx_fifo(struct nvt_dev *nvt) in nvt_clear_tx_fifo() argument
372 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); in nvt_clear_tx_fifo()
373 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); in nvt_clear_tx_fifo()
377 static void nvt_set_cir_iren(struct nvt_dev *nvt) in nvt_set_cir_iren() argument
382 nvt_cir_reg_write(nvt, iren, CIR_IREN); in nvt_set_cir_iren()
385 static void nvt_cir_regs_init(struct nvt_dev *nvt) in nvt_cir_regs_init() argument
388 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); in nvt_cir_regs_init()
389 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); in nvt_cir_regs_init()
392 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | in nvt_cir_regs_init()
399 nvt_cir_reg_write(nvt, in nvt_cir_regs_init()
405 nvt_clear_cir_fifo(nvt); in nvt_cir_regs_init()
406 nvt_clear_tx_fifo(nvt); in nvt_cir_regs_init()
409 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); in nvt_cir_regs_init()
412 nvt_set_cir_iren(nvt); in nvt_cir_regs_init()
415 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) in nvt_cir_wake_regs_init() argument
418 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES, in nvt_cir_wake_regs_init()
422 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE, in nvt_cir_wake_regs_init()
426 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH); in nvt_cir_wake_regs_init()
427 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL); in nvt_cir_wake_regs_init()
430 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV, in nvt_cir_wake_regs_init()
437 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | in nvt_cir_wake_regs_init()
443 nvt_clear_cir_wake_fifo(nvt); in nvt_cir_wake_regs_init()
446 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); in nvt_cir_wake_regs_init()
449 static void nvt_enable_wake(struct nvt_dev *nvt) in nvt_enable_wake() argument
451 nvt_efm_enable(nvt); in nvt_enable_wake()
453 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); in nvt_enable_wake()
454 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); in nvt_enable_wake()
455 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); in nvt_enable_wake()
457 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); in nvt_enable_wake()
458 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_enable_wake()
460 nvt_efm_disable(nvt); in nvt_enable_wake()
462 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | in nvt_enable_wake()
466 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); in nvt_enable_wake()
467 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); in nvt_enable_wake()
472 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
477 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
478 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
480 for (i = 0; i < nvt->pkts; i++) {
481 if (nvt->buf[i] & BUF_PULSE_BIT)
482 duration += nvt->buf[i] & BUF_LEN_MASK;
513 struct nvt_dev *nvt = dev->priv; in nvt_set_tx_carrier() local
519 nvt_cir_reg_write(nvt, 1, CIR_CP); in nvt_set_tx_carrier()
521 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); in nvt_set_tx_carrier()
524 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); in nvt_set_tx_carrier()
549 struct nvt_dev *nvt = dev->priv; in nvt_tx_ir() local
555 spin_lock_irqsave(&nvt->tx.lock, flags); in nvt_tx_ir()
558 nvt->tx.buf_count = (ret * sizeof(unsigned)); in nvt_tx_ir()
560 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); in nvt_tx_ir()
562 nvt->tx.cur_buf_num = 0; in nvt_tx_ir()
565 iren = nvt_cir_reg_read(nvt, CIR_IREN); in nvt_tx_ir()
568 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); in nvt_tx_ir()
570 nvt->tx.tx_state = ST_TX_REPLY; in nvt_tx_ir()
572 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | in nvt_tx_ir()
577 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); in nvt_tx_ir()
579 spin_unlock_irqrestore(&nvt->tx.lock, flags); in nvt_tx_ir()
581 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); in nvt_tx_ir()
583 spin_lock_irqsave(&nvt->tx.lock, flags); in nvt_tx_ir()
584 nvt->tx.tx_state = ST_TX_NONE; in nvt_tx_ir()
585 spin_unlock_irqrestore(&nvt->tx.lock, flags); in nvt_tx_ir()
588 nvt_cir_reg_write(nvt, iren, CIR_IREN); in nvt_tx_ir()
594 static void nvt_dump_rx_buf(struct nvt_dev *nvt) in nvt_dump_rx_buf() argument
598 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); in nvt_dump_rx_buf()
599 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) in nvt_dump_rx_buf()
600 printk(KERN_CONT "0x%02x ", nvt->buf[i]); in nvt_dump_rx_buf()
616 static void nvt_process_rx_ir_data(struct nvt_dev *nvt) in nvt_process_rx_ir_data() argument
625 nvt_dump_rx_buf(nvt); in nvt_process_rx_ir_data()
627 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts); in nvt_process_rx_ir_data()
631 for (i = 0; i < nvt->pkts; i++) { in nvt_process_rx_ir_data()
632 sample = nvt->buf[i]; in nvt_process_rx_ir_data()
641 ir_raw_event_store_with_filter(nvt->rdev, &rawir); in nvt_process_rx_ir_data()
648 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) { in nvt_process_rx_ir_data()
650 ir_raw_event_handle(nvt->rdev); in nvt_process_rx_ir_data()
654 nvt->pkts = 0; in nvt_process_rx_ir_data()
657 ir_raw_event_handle(nvt->rdev); in nvt_process_rx_ir_data()
662 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) in nvt_handle_rx_fifo_overrun() argument
666 nvt->pkts = 0; in nvt_handle_rx_fifo_overrun()
667 nvt_clear_cir_fifo(nvt); in nvt_handle_rx_fifo_overrun()
668 ir_raw_event_reset(nvt->rdev); in nvt_handle_rx_fifo_overrun()
672 static void nvt_get_rx_ir_data(struct nvt_dev *nvt) in nvt_get_rx_ir_data() argument
681 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); in nvt_get_rx_ir_data()
693 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_get_rx_ir_data()
695 b_idx = nvt->pkts; in nvt_get_rx_ir_data()
699 nvt_process_rx_ir_data(nvt); in nvt_get_rx_ir_data()
705 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO); in nvt_get_rx_ir_data()
706 nvt->buf[b_idx + i] = val; in nvt_get_rx_ir_data()
709 nvt->pkts += fifocount; in nvt_get_rx_ir_data()
710 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); in nvt_get_rx_ir_data()
712 nvt_process_rx_ir_data(nvt); in nvt_get_rx_ir_data()
715 nvt_handle_rx_fifo_overrun(nvt); in nvt_get_rx_ir_data()
717 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_get_rx_ir_data()
737 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) in nvt_cir_tx_inactive() argument
743 spin_lock_irqsave(&nvt->tx.lock, flags); in nvt_cir_tx_inactive()
744 tx_state = nvt->tx.tx_state; in nvt_cir_tx_inactive()
745 spin_unlock_irqrestore(&nvt->tx.lock, flags); in nvt_cir_tx_inactive()
755 struct nvt_dev *nvt = data; in nvt_cir_isr() local
761 nvt_efm_enable(nvt); in nvt_cir_isr()
762 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); in nvt_cir_isr()
763 nvt_efm_disable(nvt); in nvt_cir_isr()
778 status = nvt_cir_reg_read(nvt, CIR_IRSTS); in nvt_cir_isr()
781 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); in nvt_cir_isr()
786 nvt_cir_reg_write(nvt, status, CIR_IRSTS); in nvt_cir_isr()
787 nvt_cir_reg_write(nvt, 0, CIR_IRSTS); in nvt_cir_isr()
790 iren = nvt_cir_reg_read(nvt, CIR_IREN); in nvt_cir_isr()
802 if (nvt_cir_tx_inactive(nvt)) in nvt_cir_isr()
803 nvt_get_rx_ir_data(nvt); in nvt_cir_isr()
807 if (nvt_cir_tx_inactive(nvt)) in nvt_cir_isr()
808 nvt_get_rx_ir_data(nvt); in nvt_cir_isr()
810 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_cir_isr()
812 cur_state = nvt->study_state; in nvt_cir_isr()
814 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_cir_isr()
817 nvt_clear_cir_fifo(nvt); in nvt_cir_isr()
821 nvt_clear_tx_fifo(nvt); in nvt_cir_isr()
827 spin_lock_irqsave(&nvt->tx.lock, flags); in nvt_cir_isr()
829 pos = nvt->tx.cur_buf_num; in nvt_cir_isr()
830 count = nvt->tx.buf_count; in nvt_cir_isr()
834 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); in nvt_cir_isr()
835 nvt->tx.cur_buf_num++; in nvt_cir_isr()
838 tmp = nvt_cir_reg_read(nvt, CIR_IREN); in nvt_cir_isr()
839 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); in nvt_cir_isr()
842 spin_unlock_irqrestore(&nvt->tx.lock, flags); in nvt_cir_isr()
847 spin_lock_irqsave(&nvt->tx.lock, flags); in nvt_cir_isr()
848 if (nvt->tx.tx_state == ST_TX_REPLY) { in nvt_cir_isr()
849 nvt->tx.tx_state = ST_TX_REQUEST; in nvt_cir_isr()
850 wake_up(&nvt->tx.queue); in nvt_cir_isr()
852 spin_unlock_irqrestore(&nvt->tx.lock, flags); in nvt_cir_isr()
863 struct nvt_dev *nvt = data; in nvt_cir_wake_isr() local
868 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS); in nvt_cir_wake_isr()
873 nvt_clear_cir_wake_fifo(nvt); in nvt_cir_wake_isr()
875 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS); in nvt_cir_wake_isr()
876 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS); in nvt_cir_wake_isr()
879 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN); in nvt_cir_wake_isr()
886 (nvt->wake_state == ST_WAKE_START)) { in nvt_cir_wake_isr()
887 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) { in nvt_cir_wake_isr()
888 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); in nvt_cir_wake_isr()
892 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); in nvt_cir_wake_isr()
893 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_cir_wake_isr()
894 nvt->wake_state = ST_WAKE_FINISH; in nvt_cir_wake_isr()
895 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_cir_wake_isr()
902 static void nvt_enable_cir(struct nvt_dev *nvt) in nvt_enable_cir() argument
905 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | in nvt_enable_cir()
909 nvt_efm_enable(nvt); in nvt_enable_cir()
912 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); in nvt_enable_cir()
913 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_enable_cir()
915 nvt_efm_disable(nvt); in nvt_enable_cir()
918 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); in nvt_enable_cir()
921 nvt_set_cir_iren(nvt); in nvt_enable_cir()
924 static void nvt_disable_cir(struct nvt_dev *nvt) in nvt_disable_cir() argument
927 nvt_cir_reg_write(nvt, 0, CIR_IREN); in nvt_disable_cir()
930 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); in nvt_disable_cir()
933 nvt_cir_reg_write(nvt, 0, CIR_IRCON); in nvt_disable_cir()
936 nvt_clear_cir_fifo(nvt); in nvt_disable_cir()
937 nvt_clear_tx_fifo(nvt); in nvt_disable_cir()
939 nvt_efm_enable(nvt); in nvt_disable_cir()
942 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); in nvt_disable_cir()
943 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); in nvt_disable_cir()
945 nvt_efm_disable(nvt); in nvt_disable_cir()
950 struct nvt_dev *nvt = dev->priv; in nvt_open() local
953 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_open()
954 nvt_enable_cir(nvt); in nvt_open()
955 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_open()
962 struct nvt_dev *nvt = dev->priv; in nvt_close() local
965 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_close()
966 nvt_disable_cir(nvt); in nvt_close()
967 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_close()
973 struct nvt_dev *nvt; in nvt_probe() local
977 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL); in nvt_probe()
978 if (!nvt) in nvt_probe()
1011 nvt->cir_addr = pnp_port_start(pdev, 0); in nvt_probe()
1012 nvt->cir_irq = pnp_irq(pdev, 0); in nvt_probe()
1014 nvt->cir_wake_addr = pnp_port_start(pdev, 1); in nvt_probe()
1016 nvt->cir_wake_irq = nvt->cir_irq; in nvt_probe()
1018 nvt->cr_efir = CR_EFIR; in nvt_probe()
1019 nvt->cr_efdr = CR_EFDR; in nvt_probe()
1021 spin_lock_init(&nvt->nvt_lock); in nvt_probe()
1022 spin_lock_init(&nvt->tx.lock); in nvt_probe()
1024 pnp_set_drvdata(pdev, nvt); in nvt_probe()
1025 nvt->pdev = pdev; in nvt_probe()
1027 init_waitqueue_head(&nvt->tx.queue); in nvt_probe()
1029 ret = nvt_hw_detect(nvt); in nvt_probe()
1034 nvt_efm_enable(nvt); in nvt_probe()
1035 nvt_cir_ldev_init(nvt); in nvt_probe()
1036 nvt_cir_wake_ldev_init(nvt); in nvt_probe()
1037 nvt_efm_disable(nvt); in nvt_probe()
1040 nvt_cir_regs_init(nvt); in nvt_probe()
1041 nvt_cir_wake_regs_init(nvt); in nvt_probe()
1044 rdev->priv = nvt; in nvt_probe()
1055 rdev->input_id.product = nvt->chip_major; in nvt_probe()
1056 rdev->input_id.version = nvt->chip_minor; in nvt_probe()
1069 nvt->rdev = rdev; in nvt_probe()
1077 if (!request_region(nvt->cir_addr, in nvt_probe()
1081 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED, in nvt_probe()
1082 NVT_DRIVER_NAME, (void *)nvt)) in nvt_probe()
1085 if (!request_region(nvt->cir_wake_addr, in nvt_probe()
1089 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED, in nvt_probe()
1090 NVT_DRIVER_NAME, (void *)nvt)) in nvt_probe()
1097 cir_dump_regs(nvt); in nvt_probe()
1098 cir_wake_dump_regs(nvt); in nvt_probe()
1104 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); in nvt_probe()
1106 free_irq(nvt->cir_irq, nvt); in nvt_probe()
1108 release_region(nvt->cir_addr, CIR_IOREG_LENGTH); in nvt_probe()
1114 kfree(nvt); in nvt_probe()
1121 struct nvt_dev *nvt = pnp_get_drvdata(pdev); in nvt_remove() local
1124 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_remove()
1126 nvt_cir_reg_write(nvt, 0, CIR_IREN); in nvt_remove()
1127 nvt_disable_cir(nvt); in nvt_remove()
1129 nvt_enable_wake(nvt); in nvt_remove()
1130 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_remove()
1133 free_irq(nvt->cir_irq, nvt); in nvt_remove()
1134 free_irq(nvt->cir_wake_irq, nvt); in nvt_remove()
1135 release_region(nvt->cir_addr, CIR_IOREG_LENGTH); in nvt_remove()
1136 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); in nvt_remove()
1138 rc_unregister_device(nvt->rdev); in nvt_remove()
1140 kfree(nvt); in nvt_remove()
1145 struct nvt_dev *nvt = pnp_get_drvdata(pdev); in nvt_suspend() local
1151 spin_lock_irqsave(&nvt->nvt_lock, flags); in nvt_suspend()
1152 nvt->study_state = ST_STUDY_NONE; in nvt_suspend()
1153 nvt->wake_state = ST_WAKE_NONE; in nvt_suspend()
1154 spin_unlock_irqrestore(&nvt->nvt_lock, flags); in nvt_suspend()
1156 spin_lock_irqsave(&nvt->tx.lock, flags); in nvt_suspend()
1157 nvt->tx.tx_state = ST_TX_NONE; in nvt_suspend()
1158 spin_unlock_irqrestore(&nvt->tx.lock, flags); in nvt_suspend()
1161 nvt_cir_reg_write(nvt, 0, CIR_IREN); in nvt_suspend()
1163 nvt_efm_enable(nvt); in nvt_suspend()
1166 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); in nvt_suspend()
1167 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); in nvt_suspend()
1169 nvt_efm_disable(nvt); in nvt_suspend()
1172 nvt_enable_wake(nvt); in nvt_suspend()
1179 struct nvt_dev *nvt = pnp_get_drvdata(pdev); in nvt_resume() local
1184 nvt_set_cir_iren(nvt); in nvt_resume()
1187 nvt_efm_enable(nvt); in nvt_resume()
1188 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); in nvt_resume()
1189 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_resume()
1191 nvt_efm_disable(nvt); in nvt_resume()
1193 nvt_cir_regs_init(nvt); in nvt_resume()
1194 nvt_cir_wake_regs_init(nvt); in nvt_resume()
1201 struct nvt_dev *nvt = pnp_get_drvdata(pdev); in nvt_shutdown() local
1202 nvt_enable_wake(nvt); in nvt_shutdown()