Lines Matching refs:nvt_cr_write
43 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) in nvt_cr_write() function
60 nvt_cr_write(nvt, tmp, reg); in nvt_set_reg_bit()
67 nvt_cr_write(nvt, tmp, reg); in nvt_clear_reg_bit()
308 nvt_cr_write(nvt, val, psreg); in nvt_cir_ldev_init()
312 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_cir_ldev_init()
314 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI); in nvt_cir_ldev_init()
315 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO); in nvt_cir_ldev_init()
317 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); in nvt_cir_ldev_init()
327 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_cir_wake_ldev_init()
337 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_cir_wake_ldev_init()
339 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI); in nvt_cir_wake_ldev_init()
340 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO); in nvt_cir_wake_ldev_init()
342 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC); in nvt_cir_wake_ldev_init()
458 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_enable_wake()
913 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_enable_cir()
943 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); in nvt_disable_cir()
1167 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); in nvt_suspend()
1189 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); in nvt_resume()