Lines Matching refs:writel
298 writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); in set_lpmode()
846 writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); in get_temperature_level()
852 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); in get_temperature_level()
876 writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); in setup_registers()
877 writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); in setup_registers()
878 writel(regs->pwr_mgmt_ctrl_shdw, in setup_registers()
884 writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); in setup_registers()
885 writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); in setup_registers()
886 writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); in setup_registers()
910 writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); in setup_volt_sensitive_regs()
948 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); in setup_temperature_sensitive_regs()
949 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); in setup_temperature_sensitive_regs()
950 writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); in setup_temperature_sensitive_regs()
1022 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); in emif_interrupt_handler()
1038 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); in emif_interrupt_handler()
1083 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS), in clear_all_interrupts()
1086 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS), in clear_all_interrupts()
1095 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET), in disable_and_clear_all_interrupts()
1098 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET), in disable_and_clear_all_interrupts()
1118 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET); in setup_interrupts()
1124 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET); in setup_interrupts()
1154 writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL); in emif_onetime_settings()
1159 writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); in emif_onetime_settings()
1170 writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG); in emif_onetime_settings()
1178 writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW); in emif_onetime_settings()
1179 writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW); in emif_onetime_settings()
1180 writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW); in emif_onetime_settings()
1181 writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW); in emif_onetime_settings()
1182 writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW); in emif_onetime_settings()
1183 writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW); in emif_onetime_settings()
1184 writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW); in emif_onetime_settings()
1185 writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW); in emif_onetime_settings()
1186 writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW); in emif_onetime_settings()
1187 writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW); in emif_onetime_settings()
1188 writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW); in emif_onetime_settings()
1189 writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW); in emif_onetime_settings()
1190 writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW); in emif_onetime_settings()
1191 writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW); in emif_onetime_settings()
1192 writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW); in emif_onetime_settings()
1193 writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW); in emif_onetime_settings()
1194 writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW); in emif_onetime_settings()
1195 writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW); in emif_onetime_settings()
1196 writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW); in emif_onetime_settings()
1197 writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW); in emif_onetime_settings()
1198 writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW); in emif_onetime_settings()