69 	u32 value;  in tegra_mc_setup_latency_allowance()  local
75 	value = readl(mc->regs + MC_EMEM_ARB_CFG);  in tegra_mc_setup_latency_allowance()
76 	value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;  in tegra_mc_setup_latency_allowance()
77 	value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);  in tegra_mc_setup_latency_allowance()
78 	writel(value, mc->regs + MC_EMEM_ARB_CFG);  in tegra_mc_setup_latency_allowance()
83 		u32 value;  in tegra_mc_setup_latency_allowance()  local
85 		value = readl(mc->regs + la->reg);  in tegra_mc_setup_latency_allowance()
86 		value &= ~(la->mask << la->shift);  in tegra_mc_setup_latency_allowance()
87 		value |= (la->def & la->mask) << la->shift;  in tegra_mc_setup_latency_allowance()
88 		writel(value, mc->regs + la->reg);  in tegra_mc_setup_latency_allowance()
131 		u32 value;  in tegra_mc_irq()  local
133 		value = mc_readl(mc, MC_ERR_STATUS);  in tegra_mc_irq()
137 			addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &  in tegra_mc_irq()
143 		if (value & MC_ERR_STATUS_RW)  in tegra_mc_irq()
148 		if (value & MC_ERR_STATUS_SECURITY)  in tegra_mc_irq()
153 		id = value & MC_ERR_STATUS_CLIENT_MASK;  in tegra_mc_irq()
162 		type = (value & MC_ERR_STATUS_TYPE_MASK) >>  in tegra_mc_irq()
166 		switch (value & MC_ERR_STATUS_TYPE_MASK) {  in tegra_mc_irq()
171 			if (value & MC_ERR_STATUS_READABLE)  in tegra_mc_irq()
176 			if (value & MC_ERR_STATUS_WRITABLE)  in tegra_mc_irq()
181 			if (value & MC_ERR_STATUS_NONSECURE)  in tegra_mc_irq()
195 		value = mc_readl(mc, MC_ERR_ADR);  in tegra_mc_irq()
196 		addr |= value;  in tegra_mc_irq()
214 	u32 value;  in tegra_mc_probe()  local
274 	value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |  in tegra_mc_probe()
278 	mc_writel(mc, value, MC_INTMASK);  in tegra_mc_probe()