226 #define MBOX_BIT BIT  macro
227 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
792 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in db8500_prcmu_set_power_state()
801 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_power_state()
835 		while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in config_wakeups()
840 		writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in config_wakeups()
905 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_arm_opp()
912 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_arm_opp()
1031 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_ape_opp()
1039 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_ape_opp()
1096 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_request_ape_opp_100_voltage()
1101 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_request_ape_opp_100_voltage()
1125 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in prcmu_release_usb_wakeup_state()
1131 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in prcmu_release_usb_wakeup_state()
1156 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in request_pll()
1162 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in request_pll()
1208 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))  in db8500_prcmu_set_epod()
1218 	writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_epod()
1305 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))  in request_sysclk()
1311 	writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);  in request_sysclk()
1995 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_esram0_deep_sleep()
2005 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_esram0_deep_sleep()
2017 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotdog()
2023 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotdog()
2035 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotmon()
2044 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotmon()
2056 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in config_hot_period()
2062 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in config_hot_period()
2088 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in prcmu_a9wdog()
2098 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in prcmu_a9wdog()
2171 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_read()
2180 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_read()
2221 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_write_masked()
2230 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_write_masked()
2367 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_modem_reset()
2371 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_modem_reset()
2388 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in ack_dbb_wakeup()
2392 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in ack_dbb_wakeup()
2437 	writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);  in read_mailbox_0()
2450 	writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);  in read_mailbox_1()
2458 	writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);  in read_mailbox_2()
2465 	writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);  in read_mailbox_3()
2492 	writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);  in read_mailbox_4()
2504 	writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);  in read_mailbox_5()
2511 	writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);  in read_mailbox_6()
2517 	writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);  in read_mailbox_7()
2544 		if (bits & MBOX_BIT(n)) {  in prcmu_irq_handler()
2545 			bits -= MBOX_BIT(n);  in prcmu_irq_handler()