55 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \  argument
56 	pci_write_config_byte(dev, vsec + 0xa, val)
74 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \  argument
75 	pci_write_config_byte(dev, vsec + 0x13, val)
93 #define EXTRACT_PPC_BIT(val, bit)	(!!(val & PPC_BIT(bit)))  argument
94 #define EXTRACT_PPC_BITS(val, bs, be)	((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))  argument
97 #define   AFUD_NUM_INTS_PER_PROC(val)	EXTRACT_PPC_BITS(val,  0, 15)  argument
98 #define   AFUD_NUM_PROCS(val)		EXTRACT_PPC_BITS(val, 16, 31)  argument
99 #define   AFUD_NUM_CRS(val)		EXTRACT_PPC_BITS(val, 32, 47)  argument
100 #define   AFUD_MULTIMODE(val)		EXTRACT_PPC_BIT(val, 48)  argument
101 #define   AFUD_PUSH_BLOCK_TRANSFER(val)	EXTRACT_PPC_BIT(val, 55)  argument
102 #define   AFUD_DEDICATED_PROCESS(val)	EXTRACT_PPC_BIT(val, 59)  argument
103 #define   AFUD_AFU_DIRECTED(val)	EXTRACT_PPC_BIT(val, 61)  argument
104 #define   AFUD_TIME_SLICED(val)		EXTRACT_PPC_BIT(val, 63)  argument
106 #define   AFUD_CR_LEN(val)		EXTRACT_PPC_BITS(val, 8, 63)  argument
109 #define   AFUD_PPPSA_PP(val)		EXTRACT_PPC_BIT(val, 6)  argument
110 #define   AFUD_PPPSA_PSA(val)		EXTRACT_PPC_BIT(val, 7)  argument
111 #define   AFUD_PPPSA_LEN(val)		EXTRACT_PPC_BITS(val, 8, 63)  argument
114 #define   AFUD_EB_LEN(val)		EXTRACT_PPC_BITS(val, 8, 63)  argument
120 	u32 val;  in cxl_afu_cr_read16()  local
122 	val = cxl_afu_cr_read32(afu, cr, aligned_off);  in cxl_afu_cr_read16()
123 	return (val >> ((off & 0x2) * 8)) & 0xffff;  in cxl_afu_cr_read16()
129 	u32 val;  in cxl_afu_cr_read8()  local
131 	val = cxl_afu_cr_read32(afu, cr, aligned_off);  in cxl_afu_cr_read8()
132 	return (val >> ((off & 0x3) * 8)) & 0xff;  in cxl_afu_cr_read8()
173 	u16 val;  in find_cxl_vsec()  local
176 		pci_read_config_word(dev, vsec + 0x4, &val);  in find_cxl_vsec()
177 		if (val == CXL_PCI_VSEC_ID)  in find_cxl_vsec()
187 	u32 val;  in dump_cxl_config_space()  local
191 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);  in dump_cxl_config_space()
192 	dev_info(&dev->dev, "BAR0: %#.8x\n", val);  in dump_cxl_config_space()
193 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);  in dump_cxl_config_space()
194 	dev_info(&dev->dev, "BAR1: %#.8x\n", val);  in dump_cxl_config_space()
195 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);  in dump_cxl_config_space()
196 	dev_info(&dev->dev, "BAR2: %#.8x\n", val);  in dump_cxl_config_space()
197 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);  in dump_cxl_config_space()
198 	dev_info(&dev->dev, "BAR3: %#.8x\n", val);  in dump_cxl_config_space()
199 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);  in dump_cxl_config_space()
200 	dev_info(&dev->dev, "BAR4: %#.8x\n", val);  in dump_cxl_config_space()
201 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);  in dump_cxl_config_space()
202 	dev_info(&dev->dev, "BAR5: %#.8x\n", val);  in dump_cxl_config_space()
217 	pci_read_config_dword(dev, vsec + 0x0, &val);  in dump_cxl_config_space()
218 	show_reg("Cap ID", (val >> 0) & 0xffff);  in dump_cxl_config_space()
219 	show_reg("Cap Ver", (val >> 16) & 0xf);  in dump_cxl_config_space()
220 	show_reg("Next Cap Ptr", (val >> 20) & 0xfff);  in dump_cxl_config_space()
221 	pci_read_config_dword(dev, vsec + 0x4, &val);  in dump_cxl_config_space()
222 	show_reg("VSEC ID", (val >> 0) & 0xffff);  in dump_cxl_config_space()
223 	show_reg("VSEC Rev", (val >> 16) & 0xf);  in dump_cxl_config_space()
224 	show_reg("VSEC Length",	(val >> 20) & 0xfff);  in dump_cxl_config_space()
225 	pci_read_config_dword(dev, vsec + 0x8, &val);  in dump_cxl_config_space()
226 	show_reg("Num AFUs", (val >> 0) & 0xff);  in dump_cxl_config_space()
227 	show_reg("Status", (val >> 8) & 0xff);  in dump_cxl_config_space()
228 	show_reg("Mode Control", (val >> 16) & 0xff);  in dump_cxl_config_space()
229 	show_reg("Reserved", (val >> 24) & 0xff);  in dump_cxl_config_space()
230 	pci_read_config_dword(dev, vsec + 0xc, &val);  in dump_cxl_config_space()
231 	show_reg("PSL Rev", (val >> 0) & 0xffff);  in dump_cxl_config_space()
232 	show_reg("CAIA Ver", (val >> 16) & 0xffff);  in dump_cxl_config_space()
233 	pci_read_config_dword(dev, vsec + 0x10, &val);  in dump_cxl_config_space()
234 	show_reg("Base Image Rev", (val >> 0) & 0xffff);  in dump_cxl_config_space()
235 	show_reg("Reserved", (val >> 16) & 0x0fff);  in dump_cxl_config_space()
236 	show_reg("Image Control", (val >> 28) & 0x3);  in dump_cxl_config_space()
237 	show_reg("Reserved", (val >> 30) & 0x1);  in dump_cxl_config_space()
238 	show_reg("Image Loaded", (val >> 31) & 0x1);  in dump_cxl_config_space()
240 	pci_read_config_dword(dev, vsec + 0x14, &val);  in dump_cxl_config_space()
241 	show_reg("Reserved", val);  in dump_cxl_config_space()
242 	pci_read_config_dword(dev, vsec + 0x18, &val);  in dump_cxl_config_space()
243 	show_reg("Reserved", val);  in dump_cxl_config_space()
244 	pci_read_config_dword(dev, vsec + 0x1c, &val);  in dump_cxl_config_space()
245 	show_reg("Reserved", val);  in dump_cxl_config_space()
247 	pci_read_config_dword(dev, vsec + 0x20, &val);  in dump_cxl_config_space()
248 	show_reg("AFU Descriptor Offset", val);  in dump_cxl_config_space()
249 	pci_read_config_dword(dev, vsec + 0x24, &val);  in dump_cxl_config_space()
250 	show_reg("AFU Descriptor Size", val);  in dump_cxl_config_space()
251 	pci_read_config_dword(dev, vsec + 0x28, &val);  in dump_cxl_config_space()
252 	show_reg("Problem State Offset", val);  in dump_cxl_config_space()
253 	pci_read_config_dword(dev, vsec + 0x2c, &val);  in dump_cxl_config_space()
254 	show_reg("Problem State Size", val);  in dump_cxl_config_space()
256 	pci_read_config_dword(dev, vsec + 0x30, &val);  in dump_cxl_config_space()
257 	show_reg("Reserved", val);  in dump_cxl_config_space()
258 	pci_read_config_dword(dev, vsec + 0x34, &val);  in dump_cxl_config_space()
259 	show_reg("Reserved", val);  in dump_cxl_config_space()
260 	pci_read_config_dword(dev, vsec + 0x38, &val);  in dump_cxl_config_space()
261 	show_reg("Reserved", val);  in dump_cxl_config_space()
262 	pci_read_config_dword(dev, vsec + 0x3c, &val);  in dump_cxl_config_space()
263 	show_reg("Reserved", val);  in dump_cxl_config_space()
265 	pci_read_config_dword(dev, vsec + 0x40, &val);  in dump_cxl_config_space()
266 	show_reg("PSL Programming Port", val);  in dump_cxl_config_space()
267 	pci_read_config_dword(dev, vsec + 0x44, &val);  in dump_cxl_config_space()
268 	show_reg("PSL Programming Control", val);  in dump_cxl_config_space()
270 	pci_read_config_dword(dev, vsec + 0x48, &val);  in dump_cxl_config_space()
271 	show_reg("Reserved", val);  in dump_cxl_config_space()
272 	pci_read_config_dword(dev, vsec + 0x4c, &val);  in dump_cxl_config_space()
273 	show_reg("Reserved", val);  in dump_cxl_config_space()
275 	pci_read_config_dword(dev, vsec + 0x50, &val);  in dump_cxl_config_space()
276 	show_reg("Flash Address Register", val);  in dump_cxl_config_space()
277 	pci_read_config_dword(dev, vsec + 0x54, &val);  in dump_cxl_config_space()
278 	show_reg("Flash Size Register", val);  in dump_cxl_config_space()
279 	pci_read_config_dword(dev, vsec + 0x58, &val);  in dump_cxl_config_space()
280 	show_reg("Flash Status/Control Register", val);  in dump_cxl_config_space()
281 	pci_read_config_dword(dev, vsec + 0x58, &val);  in dump_cxl_config_space()
282 	show_reg("Flash Data Port", val);  in dump_cxl_config_space()
289 	u64 val;  in dump_afu_descriptor()  local
294 	val = AFUD_READ_INFO(afu);  in dump_afu_descriptor()
295 	show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));  in dump_afu_descriptor()
296 	show_reg("num_of_processes", AFUD_NUM_PROCS(val));  in dump_afu_descriptor()
297 	show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));  in dump_afu_descriptor()
298 	show_reg("req_prog_mode", val & 0xffffULL);  in dump_afu_descriptor()
300 	val = AFUD_READ(afu, 0x8);  in dump_afu_descriptor()
301 	show_reg("Reserved", val);  in dump_afu_descriptor()
302 	val = AFUD_READ(afu, 0x10);  in dump_afu_descriptor()
303 	show_reg("Reserved", val);  in dump_afu_descriptor()
304 	val = AFUD_READ(afu, 0x18);  in dump_afu_descriptor()
305 	show_reg("Reserved", val);  in dump_afu_descriptor()
307 	val = AFUD_READ_CR(afu);  in dump_afu_descriptor()
308 	show_reg("Reserved", (val >> (63-7)) & 0xff);  in dump_afu_descriptor()
309 	show_reg("AFU_CR_len", AFUD_CR_LEN(val));  in dump_afu_descriptor()
311 	val = AFUD_READ_CR_OFF(afu);  in dump_afu_descriptor()
312 	show_reg("AFU_CR_offset", val);  in dump_afu_descriptor()
314 	val = AFUD_READ_PPPSA(afu);  in dump_afu_descriptor()
315 	show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);  in dump_afu_descriptor()
316 	show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));  in dump_afu_descriptor()
318 	val = AFUD_READ_PPPSA_OFF(afu);  in dump_afu_descriptor()
319 	show_reg("PerProcessPSA_offset", val);  in dump_afu_descriptor()
321 	val = AFUD_READ_EB(afu);  in dump_afu_descriptor()
322 	show_reg("Reserved", (val >> (63-7)) & 0xff);  in dump_afu_descriptor()
323 	show_reg("AFU_EB_len", AFUD_EB_LEN(val));  in dump_afu_descriptor()
325 	val = AFUD_READ_EB_OFF(afu);  in dump_afu_descriptor()
326 	show_reg("AFU_EB_offset", val);  in dump_afu_descriptor()
470 	u8 val;  in switch_card_to_cxl()  local
480 	if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {  in switch_card_to_cxl()
484 	val &= ~CXL_VSEC_PROTOCOL_MASK;  in switch_card_to_cxl()
485 	val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;  in switch_card_to_cxl()
486 	if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {  in switch_card_to_cxl()
572 	u64 val;  in cxl_read_afu_descriptor()  local
574 	val = AFUD_READ_INFO(afu);  in cxl_read_afu_descriptor()
575 	afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);  in cxl_read_afu_descriptor()
576 	afu->max_procs_virtualised = AFUD_NUM_PROCS(val);  in cxl_read_afu_descriptor()
577 	afu->crs_num = AFUD_NUM_CRS(val);  in cxl_read_afu_descriptor()
579 	if (AFUD_AFU_DIRECTED(val))  in cxl_read_afu_descriptor()
581 	if (AFUD_DEDICATED_PROCESS(val))  in cxl_read_afu_descriptor()
583 	if (AFUD_TIME_SLICED(val))  in cxl_read_afu_descriptor()
586 	val = AFUD_READ_PPPSA(afu);  in cxl_read_afu_descriptor()
587 	afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;  in cxl_read_afu_descriptor()
588 	afu->psa = AFUD_PPPSA_PSA(val);  in cxl_read_afu_descriptor()
589 	if ((afu->pp_psa = AFUD_PPPSA_PP(val)))  in cxl_read_afu_descriptor()
592 	val = AFUD_READ_CR(afu);  in cxl_read_afu_descriptor()
593 	afu->crs_len = AFUD_CR_LEN(val) * 256;  in cxl_read_afu_descriptor()