369 			irq_handler_t irq_handler, int cpu, int blade)  in gru_chiplet_setup_tlb_irq()  argument
400 static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)  in gru_chiplet_teardown_tlb_irq()  argument
419 			irq_handler_t irq_handler, int cpu, int blade)  in gru_chiplet_setup_tlb_irq()  argument
429 	irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);  in gru_chiplet_setup_tlb_irq()
443 	gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;  in gru_chiplet_setup_tlb_irq()
447 static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)  in gru_chiplet_teardown_tlb_irq()  argument
454 		irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];  in gru_chiplet_teardown_tlb_irq()
466 	int blade;  in gru_teardown_tlb_irqs()  local
470 		blade = uv_cpu_to_blade_id(cpu);  in gru_teardown_tlb_irqs()
471 		gru_chiplet_teardown_tlb_irq(0, cpu, blade);  in gru_teardown_tlb_irqs()
472 		gru_chiplet_teardown_tlb_irq(1, cpu, blade);  in gru_teardown_tlb_irqs()
474 	for_each_possible_blade(blade) {  in gru_teardown_tlb_irqs()
475 		if (uv_blade_nr_possible_cpus(blade))  in gru_teardown_tlb_irqs()
477 		gru_chiplet_teardown_tlb_irq(0, 0, blade);  in gru_teardown_tlb_irqs()
478 		gru_chiplet_teardown_tlb_irq(1, 0, blade);  in gru_teardown_tlb_irqs()
484 	int blade;  in gru_setup_tlb_irqs()  local
489 		blade = uv_cpu_to_blade_id(cpu);  in gru_setup_tlb_irqs()
490 		ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);  in gru_setup_tlb_irqs()
494 		ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);  in gru_setup_tlb_irqs()
498 	for_each_possible_blade(blade) {  in gru_setup_tlb_irqs()
499 		if (uv_blade_nr_possible_cpus(blade))  in gru_setup_tlb_irqs()
501 		ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);  in gru_setup_tlb_irqs()
505 		ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);  in gru_setup_tlb_irqs()