213 	void __iomem *base = host->ioaddr + (reg & ~0x3);  in esdhc_clrset_le()
223 	u32 val = readl(host->ioaddr + reg);  in esdhc_readl_le()
256 				val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;  in esdhc_readl_le()
285 			writel(SDHCI_INT_RESPONSE, host->ioaddr +  in esdhc_readl_le()
310 			data = readl(host->ioaddr + SDHCI_HOST_CONTROL);  in esdhc_writel_le()
312 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);  in esdhc_writel_le()
314 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);  in esdhc_writel_le()
322 			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writel_le()
324 			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writel_le()
331 				writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);  in esdhc_writel_le()
343 	writel(val, host->ioaddr + reg);  in esdhc_writel_le()
365 		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_readw_le()
371 				val = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_readw_le()
374 				val = readl(host->ioaddr + SDHCI_ACMD12_ERR);  in esdhc_readw_le()
389 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_readw_le()
397 			ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);  in esdhc_readw_le()
403 	return readw(host->ioaddr + reg);  in esdhc_readw_le()
414 		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writew_le()
419 		writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writew_le()
422 		new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writew_le()
427 		writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writew_le()
429 			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
434 			writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
436 			u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);  in esdhc_writew_le()
437 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
452 			writel(v, host->ioaddr + SDHCI_ACMD12_ERR);  in esdhc_writew_le()
453 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
462 			v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writew_le()
464 			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_writew_le()
468 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
475 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
494 			       host->ioaddr + SDHCI_TRANSFER_MODE);  in esdhc_writew_le()
497 			       host->ioaddr + SDHCI_TRANSFER_MODE);  in esdhc_writew_le()
560 			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writeb_le()
562 					host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writeb_le()
601 			val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_pltfm_set_clock()
603 					host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_pltfm_set_clock()
639 		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_pltfm_set_clock()
641 		host->ioaddr + ESDHC_VENDOR_SPEC);  in esdhc_pltfm_set_clock()
657 		return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &  in esdhc_pltfm_get_ro()
693 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_prepare_tuning()
696 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_prepare_tuning()
697 	writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);  in esdhc_prepare_tuning()
700 			val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));  in esdhc_prepare_tuning()
707 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_post_tuning()
709 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_post_tuning()
794 		writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |  in esdhc_set_uhs_signaling()
796 				host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_set_uhs_signaling()
805 			writel(v, host->ioaddr + ESDHC_DLL_CTRL);  in esdhc_set_uhs_signaling()
1001 		writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);  in sdhci_esdhc_imx_probe()
1011 		writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |  in sdhci_esdhc_imx_probe()
1013 			host->ioaddr + ESDHC_TUNING_CTRL);  in sdhci_esdhc_imx_probe()
1120 	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);  in sdhci_esdhc_imx_remove()