Lines Matching refs:host
260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, in sh_mmcif_bitset() argument
263 writel(val | readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitset()
266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, in sh_mmcif_bitclr() argument
269 writel(~val & readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitclr()
274 struct sh_mmcif_host *host = arg; in mmcif_dma_complete() local
275 struct mmc_request *mrq = host->mrq; in mmcif_dma_complete()
277 dev_dbg(&host->pd->dev, "Command completed\n"); in mmcif_dma_complete()
280 dev_name(&host->pd->dev))) in mmcif_dma_complete()
283 complete(&host->dma_complete); in mmcif_dma_complete()
286 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_rx() argument
288 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_rx()
291 struct dma_chan *chan = host->chan_rx; in sh_mmcif_start_dma_rx()
298 host->dma_active = true; in sh_mmcif_start_dma_rx()
305 desc->callback_param = host; in sh_mmcif_start_dma_rx()
307 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); in sh_mmcif_start_dma_rx()
310 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", in sh_mmcif_start_dma_rx()
317 host->chan_rx = NULL; in sh_mmcif_start_dma_rx()
318 host->dma_active = false; in sh_mmcif_start_dma_rx()
321 chan = host->chan_tx; in sh_mmcif_start_dma_rx()
323 host->chan_tx = NULL; in sh_mmcif_start_dma_rx()
326 dev_warn(&host->pd->dev, in sh_mmcif_start_dma_rx()
328 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_rx()
331 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, in sh_mmcif_start_dma_rx()
335 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_tx() argument
337 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_tx()
340 struct dma_chan *chan = host->chan_tx; in sh_mmcif_start_dma_tx()
347 host->dma_active = true; in sh_mmcif_start_dma_tx()
354 desc->callback_param = host; in sh_mmcif_start_dma_tx()
356 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
359 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", in sh_mmcif_start_dma_tx()
366 host->chan_tx = NULL; in sh_mmcif_start_dma_tx()
367 host->dma_active = false; in sh_mmcif_start_dma_tx()
370 chan = host->chan_rx; in sh_mmcif_start_dma_tx()
372 host->chan_rx = NULL; in sh_mmcif_start_dma_tx()
375 dev_warn(&host->pd->dev, in sh_mmcif_start_dma_tx()
377 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
380 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, in sh_mmcif_start_dma_tx()
385 sh_mmcif_request_dma_one(struct sh_mmcif_host *host, in sh_mmcif_request_dma_one() argument
405 slave_data, &host->pd->dev, in sh_mmcif_request_dma_one()
408 dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__, in sh_mmcif_request_dma_one()
414 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); in sh_mmcif_request_dma_one()
435 static void sh_mmcif_request_dma(struct sh_mmcif_host *host, in sh_mmcif_request_dma() argument
438 host->dma_active = false; in sh_mmcif_request_dma()
443 } else if (!host->pd->dev.of_node) { in sh_mmcif_request_dma()
448 host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); in sh_mmcif_request_dma()
449 if (!host->chan_tx) in sh_mmcif_request_dma()
452 host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); in sh_mmcif_request_dma()
453 if (!host->chan_rx) { in sh_mmcif_request_dma()
454 dma_release_channel(host->chan_tx); in sh_mmcif_request_dma()
455 host->chan_tx = NULL; in sh_mmcif_request_dma()
459 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) in sh_mmcif_release_dma() argument
461 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_release_dma()
463 if (host->chan_tx) { in sh_mmcif_release_dma()
464 struct dma_chan *chan = host->chan_tx; in sh_mmcif_release_dma()
465 host->chan_tx = NULL; in sh_mmcif_release_dma()
468 if (host->chan_rx) { in sh_mmcif_release_dma()
469 struct dma_chan *chan = host->chan_rx; in sh_mmcif_release_dma()
470 host->chan_rx = NULL; in sh_mmcif_release_dma()
474 host->dma_active = false; in sh_mmcif_release_dma()
477 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) in sh_mmcif_clock_control() argument
479 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; in sh_mmcif_clock_control()
482 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
483 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); in sh_mmcif_clock_control()
487 if (sup_pclk && clk == host->clk) in sh_mmcif_clock_control()
488 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); in sh_mmcif_clock_control()
490 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & in sh_mmcif_clock_control()
491 ((fls(DIV_ROUND_UP(host->clk, in sh_mmcif_clock_control()
494 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
497 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) in sh_mmcif_sync_reset() argument
501 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); in sh_mmcif_sync_reset()
503 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); in sh_mmcif_sync_reset()
504 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); in sh_mmcif_sync_reset()
505 if (host->ccs_enable) in sh_mmcif_sync_reset()
507 if (host->clk_ctrl2_enable) in sh_mmcif_sync_reset()
508 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); in sh_mmcif_sync_reset()
509 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | in sh_mmcif_sync_reset()
512 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); in sh_mmcif_sync_reset()
515 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) in sh_mmcif_error_manage() argument
520 host->sd_error = false; in sh_mmcif_error_manage()
522 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); in sh_mmcif_error_manage()
523 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); in sh_mmcif_error_manage()
524 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); in sh_mmcif_error_manage()
525 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); in sh_mmcif_error_manage()
528 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); in sh_mmcif_error_manage()
529 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); in sh_mmcif_error_manage()
531 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) in sh_mmcif_error_manage()
537 dev_err(&host->pd->dev, in sh_mmcif_error_manage()
541 sh_mmcif_sync_reset(host); in sh_mmcif_error_manage()
542 dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); in sh_mmcif_error_manage()
547 dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", in sh_mmcif_error_manage()
548 host->state, host->wait_for); in sh_mmcif_error_manage()
551 dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", in sh_mmcif_error_manage()
552 host->state, host->wait_for); in sh_mmcif_error_manage()
555 dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", in sh_mmcif_error_manage()
556 host->state, host->wait_for); in sh_mmcif_error_manage()
562 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) in sh_mmcif_next_block() argument
564 struct mmc_data *data = host->mrq->data; in sh_mmcif_next_block()
566 host->sg_blkidx += host->blocksize; in sh_mmcif_next_block()
569 BUG_ON(host->sg_blkidx > data->sg->length); in sh_mmcif_next_block()
571 if (host->sg_blkidx == data->sg->length) { in sh_mmcif_next_block()
572 host->sg_blkidx = 0; in sh_mmcif_next_block()
573 if (++host->sg_idx < data->sg_len) in sh_mmcif_next_block()
574 host->pio_ptr = sg_virt(++data->sg); in sh_mmcif_next_block()
576 host->pio_ptr = p; in sh_mmcif_next_block()
579 return host->sg_idx != data->sg_len; in sh_mmcif_next_block()
582 static void sh_mmcif_single_read(struct sh_mmcif_host *host, in sh_mmcif_single_read() argument
585 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_read()
588 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
591 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_single_read()
594 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) in sh_mmcif_read_block() argument
596 struct mmc_data *data = host->mrq->data; in sh_mmcif_read_block()
600 if (host->sd_error) { in sh_mmcif_read_block()
601 data->error = sh_mmcif_error_manage(host); in sh_mmcif_read_block()
602 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); in sh_mmcif_read_block()
606 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_read_block()
607 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_read_block()
610 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); in sh_mmcif_read_block()
611 host->wait_for = MMCIF_WAIT_FOR_READ_END; in sh_mmcif_read_block()
616 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, in sh_mmcif_multi_read() argument
624 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_read()
627 host->wait_for = MMCIF_WAIT_FOR_MREAD; in sh_mmcif_multi_read()
628 host->sg_idx = 0; in sh_mmcif_multi_read()
629 host->sg_blkidx = 0; in sh_mmcif_multi_read()
630 host->pio_ptr = sg_virt(data->sg); in sh_mmcif_multi_read()
632 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_multi_read()
635 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) in sh_mmcif_mread_block() argument
637 struct mmc_data *data = host->mrq->data; in sh_mmcif_mread_block()
638 u32 *p = host->pio_ptr; in sh_mmcif_mread_block()
641 if (host->sd_error) { in sh_mmcif_mread_block()
642 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mread_block()
643 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); in sh_mmcif_mread_block()
649 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mread_block()
650 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_mread_block()
652 if (!sh_mmcif_next_block(host, p)) in sh_mmcif_mread_block()
655 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_mread_block()
660 static void sh_mmcif_single_write(struct sh_mmcif_host *host, in sh_mmcif_single_write() argument
663 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_write()
666 host->wait_for = MMCIF_WAIT_FOR_WRITE; in sh_mmcif_single_write()
669 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_single_write()
672 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) in sh_mmcif_write_block() argument
674 struct mmc_data *data = host->mrq->data; in sh_mmcif_write_block()
678 if (host->sd_error) { in sh_mmcif_write_block()
679 data->error = sh_mmcif_error_manage(host); in sh_mmcif_write_block()
680 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); in sh_mmcif_write_block()
684 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_write_block()
685 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_write_block()
688 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); in sh_mmcif_write_block()
689 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; in sh_mmcif_write_block()
694 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, in sh_mmcif_multi_write() argument
702 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_write()
705 host->wait_for = MMCIF_WAIT_FOR_MWRITE; in sh_mmcif_multi_write()
706 host->sg_idx = 0; in sh_mmcif_multi_write()
707 host->sg_blkidx = 0; in sh_mmcif_multi_write()
708 host->pio_ptr = sg_virt(data->sg); in sh_mmcif_multi_write()
710 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_multi_write()
713 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) in sh_mmcif_mwrite_block() argument
715 struct mmc_data *data = host->mrq->data; in sh_mmcif_mwrite_block()
716 u32 *p = host->pio_ptr; in sh_mmcif_mwrite_block()
719 if (host->sd_error) { in sh_mmcif_mwrite_block()
720 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mwrite_block()
721 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); in sh_mmcif_mwrite_block()
727 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mwrite_block()
728 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_mwrite_block()
730 if (!sh_mmcif_next_block(host, p)) in sh_mmcif_mwrite_block()
733 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_mwrite_block()
738 static void sh_mmcif_get_response(struct sh_mmcif_host *host, in sh_mmcif_get_response() argument
742 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); in sh_mmcif_get_response()
743 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); in sh_mmcif_get_response()
744 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); in sh_mmcif_get_response()
745 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
747 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
750 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, in sh_mmcif_get_cmd12response() argument
753 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); in sh_mmcif_get_cmd12response()
756 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, in sh_mmcif_set_cmd() argument
778 dev_err(&host->pd->dev, "Unsupported response type.\n"); in sh_mmcif_set_cmd()
795 switch (host->bus_width) { in sh_mmcif_set_cmd()
806 dev_err(&host->pd->dev, "Unsupported bus width.\n"); in sh_mmcif_set_cmd()
809 switch (host->timing) { in sh_mmcif_set_cmd()
828 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, in sh_mmcif_set_cmd()
846 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, in sh_mmcif_data_trans() argument
851 sh_mmcif_multi_read(host, mrq); in sh_mmcif_data_trans()
854 sh_mmcif_multi_write(host, mrq); in sh_mmcif_data_trans()
857 sh_mmcif_single_write(host, mrq); in sh_mmcif_data_trans()
861 sh_mmcif_single_read(host, mrq); in sh_mmcif_data_trans()
864 dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); in sh_mmcif_data_trans()
869 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, in sh_mmcif_start_cmd() argument
892 if (host->ccs_enable) in sh_mmcif_start_cmd()
896 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); in sh_mmcif_start_cmd()
897 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, in sh_mmcif_start_cmd()
900 opc = sh_mmcif_set_cmd(host, mrq); in sh_mmcif_start_cmd()
902 if (host->ccs_enable) in sh_mmcif_start_cmd()
903 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); in sh_mmcif_start_cmd()
905 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); in sh_mmcif_start_cmd()
906 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); in sh_mmcif_start_cmd()
908 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); in sh_mmcif_start_cmd()
910 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_start_cmd()
911 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); in sh_mmcif_start_cmd()
913 host->wait_for = MMCIF_WAIT_FOR_CMD; in sh_mmcif_start_cmd()
914 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_start_cmd()
915 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_start_cmd()
918 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, in sh_mmcif_stop_cmd() argument
923 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); in sh_mmcif_stop_cmd()
926 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); in sh_mmcif_stop_cmd()
929 dev_err(&host->pd->dev, "unsupported stop cmd\n"); in sh_mmcif_stop_cmd()
930 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_stop_cmd()
934 host->wait_for = MMCIF_WAIT_FOR_STOP; in sh_mmcif_stop_cmd()
939 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_request() local
942 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_request()
943 if (host->state != STATE_IDLE) { in sh_mmcif_request()
944 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); in sh_mmcif_request()
945 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
951 host->state = STATE_REQUEST; in sh_mmcif_request()
952 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
962 host->state = STATE_IDLE; in sh_mmcif_request()
970 host->mrq = mrq; in sh_mmcif_request()
972 sh_mmcif_start_cmd(host, mrq); in sh_mmcif_request()
975 static int sh_mmcif_clk_update(struct sh_mmcif_host *host) in sh_mmcif_clk_update() argument
977 int ret = clk_prepare_enable(host->hclk); in sh_mmcif_clk_update()
980 host->clk = clk_get_rate(host->hclk); in sh_mmcif_clk_update()
981 host->mmc->f_max = host->clk / 2; in sh_mmcif_clk_update()
982 host->mmc->f_min = host->clk / 512; in sh_mmcif_clk_update()
988 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) in sh_mmcif_set_power() argument
990 struct mmc_host *mmc = host->mmc; in sh_mmcif_set_power()
1000 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_set_ios() local
1003 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_set_ios()
1004 if (host->state != STATE_IDLE) { in sh_mmcif_set_ios()
1005 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); in sh_mmcif_set_ios()
1006 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1010 host->state = STATE_IOS; in sh_mmcif_set_ios()
1011 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1014 if (!host->card_present) { in sh_mmcif_set_ios()
1016 sh_mmcif_request_dma(host, host->pd->dev.platform_data); in sh_mmcif_set_ios()
1017 host->card_present = true; in sh_mmcif_set_ios()
1019 sh_mmcif_set_power(host, ios); in sh_mmcif_set_ios()
1022 sh_mmcif_clock_control(host, 0); in sh_mmcif_set_ios()
1024 if (host->card_present) { in sh_mmcif_set_ios()
1025 sh_mmcif_release_dma(host); in sh_mmcif_set_ios()
1026 host->card_present = false; in sh_mmcif_set_ios()
1029 if (host->power) { in sh_mmcif_set_ios()
1030 pm_runtime_put_sync(&host->pd->dev); in sh_mmcif_set_ios()
1031 clk_disable_unprepare(host->hclk); in sh_mmcif_set_ios()
1032 host->power = false; in sh_mmcif_set_ios()
1034 sh_mmcif_set_power(host, ios); in sh_mmcif_set_ios()
1036 host->state = STATE_IDLE; in sh_mmcif_set_ios()
1041 if (!host->power) { in sh_mmcif_set_ios()
1042 sh_mmcif_clk_update(host); in sh_mmcif_set_ios()
1043 pm_runtime_get_sync(&host->pd->dev); in sh_mmcif_set_ios()
1044 host->power = true; in sh_mmcif_set_ios()
1045 sh_mmcif_sync_reset(host); in sh_mmcif_set_ios()
1047 sh_mmcif_clock_control(host, ios->clock); in sh_mmcif_set_ios()
1050 host->timing = ios->timing; in sh_mmcif_set_ios()
1051 host->bus_width = ios->bus_width; in sh_mmcif_set_ios()
1052 host->state = STATE_IDLE; in sh_mmcif_set_ios()
1057 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_get_cd() local
1058 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; in sh_mmcif_get_cd()
1067 return p->get_cd(host->pd); in sh_mmcif_get_cd()
1076 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) in sh_mmcif_end_cmd() argument
1078 struct mmc_command *cmd = host->mrq->cmd; in sh_mmcif_end_cmd()
1079 struct mmc_data *data = host->mrq->data; in sh_mmcif_end_cmd()
1082 if (host->sd_error) { in sh_mmcif_end_cmd()
1090 cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1093 dev_dbg(&host->pd->dev, "CMD%d error %d\n", in sh_mmcif_end_cmd()
1095 host->sd_error = false; in sh_mmcif_end_cmd()
1103 sh_mmcif_get_response(host, cmd); in sh_mmcif_end_cmd()
1112 init_completion(&host->dma_complete); in sh_mmcif_end_cmd()
1115 if (host->chan_rx) in sh_mmcif_end_cmd()
1116 sh_mmcif_start_dma_rx(host); in sh_mmcif_end_cmd()
1118 if (host->chan_tx) in sh_mmcif_end_cmd()
1119 sh_mmcif_start_dma_tx(host); in sh_mmcif_end_cmd()
1122 if (!host->dma_active) { in sh_mmcif_end_cmd()
1123 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); in sh_mmcif_end_cmd()
1128 time = wait_for_completion_interruptible_timeout(&host->dma_complete, in sh_mmcif_end_cmd()
1129 host->timeout); in sh_mmcif_end_cmd()
1132 dma_unmap_sg(host->chan_rx->device->dev, in sh_mmcif_end_cmd()
1136 dma_unmap_sg(host->chan_tx->device->dev, in sh_mmcif_end_cmd()
1140 if (host->sd_error) { in sh_mmcif_end_cmd()
1141 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1144 data->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1146 dev_err(host->mmc->parent, "DMA timeout!\n"); in sh_mmcif_end_cmd()
1149 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1153 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, in sh_mmcif_end_cmd()
1155 host->dma_active = false; in sh_mmcif_end_cmd()
1161 dmaengine_terminate_all(host->chan_rx); in sh_mmcif_end_cmd()
1163 dmaengine_terminate_all(host->chan_tx); in sh_mmcif_end_cmd()
1171 struct sh_mmcif_host *host = dev_id; in sh_mmcif_irqt() local
1177 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_irqt()
1178 wait_work = host->wait_for; in sh_mmcif_irqt()
1179 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_irqt()
1181 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_irqt()
1183 mutex_lock(&host->thread_lock); in sh_mmcif_irqt()
1185 mrq = host->mrq; in sh_mmcif_irqt()
1187 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", in sh_mmcif_irqt()
1188 host->state, host->wait_for); in sh_mmcif_irqt()
1189 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1200 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1204 wait = sh_mmcif_end_cmd(host); in sh_mmcif_irqt()
1208 wait = sh_mmcif_mread_block(host); in sh_mmcif_irqt()
1212 wait = sh_mmcif_read_block(host); in sh_mmcif_irqt()
1216 wait = sh_mmcif_mwrite_block(host); in sh_mmcif_irqt()
1220 wait = sh_mmcif_write_block(host); in sh_mmcif_irqt()
1223 if (host->sd_error) { in sh_mmcif_irqt()
1224 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1225 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); in sh_mmcif_irqt()
1228 sh_mmcif_get_cmd12response(host, mrq->stop); in sh_mmcif_irqt()
1233 if (host->sd_error) { in sh_mmcif_irqt()
1234 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1235 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); in sh_mmcif_irqt()
1243 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1245 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1249 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { in sh_mmcif_irqt()
1256 sh_mmcif_stop_cmd(host, mrq); in sh_mmcif_irqt()
1258 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1259 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1265 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_irqt()
1266 host->state = STATE_IDLE; in sh_mmcif_irqt()
1267 host->mrq = NULL; in sh_mmcif_irqt()
1268 mmc_request_done(host->mmc, mrq); in sh_mmcif_irqt()
1270 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1277 struct sh_mmcif_host *host = dev_id; in sh_mmcif_intr() local
1280 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); in sh_mmcif_intr()
1281 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); in sh_mmcif_intr()
1282 if (host->ccs_enable) in sh_mmcif_intr()
1283 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); in sh_mmcif_intr()
1285 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); in sh_mmcif_intr()
1286 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); in sh_mmcif_intr()
1289 dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", in sh_mmcif_intr()
1293 host->sd_error = true; in sh_mmcif_intr()
1294 dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); in sh_mmcif_intr()
1297 if (!host->mrq) in sh_mmcif_intr()
1298 dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); in sh_mmcif_intr()
1299 if (!host->dma_active) in sh_mmcif_intr()
1301 else if (host->sd_error) in sh_mmcif_intr()
1302 mmcif_dma_complete(host); in sh_mmcif_intr()
1304 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); in sh_mmcif_intr()
1313 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); in mmcif_timeout_work() local
1314 struct mmc_request *mrq = host->mrq; in mmcif_timeout_work()
1317 if (host->dying) in mmcif_timeout_work()
1321 spin_lock_irqsave(&host->lock, flags); in mmcif_timeout_work()
1322 if (host->state == STATE_IDLE) { in mmcif_timeout_work()
1323 spin_unlock_irqrestore(&host->lock, flags); in mmcif_timeout_work()
1327 dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", in mmcif_timeout_work()
1328 host->wait_for, mrq->cmd->opcode); in mmcif_timeout_work()
1330 host->state = STATE_TIMEOUT; in mmcif_timeout_work()
1331 spin_unlock_irqrestore(&host->lock, flags); in mmcif_timeout_work()
1337 switch (host->wait_for) { in mmcif_timeout_work()
1339 mrq->cmd->error = sh_mmcif_error_manage(host); in mmcif_timeout_work()
1342 mrq->stop->error = sh_mmcif_error_manage(host); in mmcif_timeout_work()
1350 mrq->data->error = sh_mmcif_error_manage(host); in mmcif_timeout_work()
1356 host->state = STATE_IDLE; in mmcif_timeout_work()
1357 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in mmcif_timeout_work()
1358 host->mrq = NULL; in mmcif_timeout_work()
1359 mmc_request_done(host->mmc, mrq); in mmcif_timeout_work()
1362 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) in sh_mmcif_init_ocr() argument
1364 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; in sh_mmcif_init_ocr()
1365 struct mmc_host *mmc = host->mmc; in sh_mmcif_init_ocr()
1382 struct sh_mmcif_host *host; in sh_mmcif_probe() local
1408 host = mmc_priv(mmc); in sh_mmcif_probe()
1409 host->mmc = mmc; in sh_mmcif_probe()
1410 host->addr = reg; in sh_mmcif_probe()
1411 host->timeout = msecs_to_jiffies(10000); in sh_mmcif_probe()
1412 host->ccs_enable = !pd || !pd->ccs_unsupported; in sh_mmcif_probe()
1413 host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; in sh_mmcif_probe()
1415 host->pd = pdev; in sh_mmcif_probe()
1417 spin_lock_init(&host->lock); in sh_mmcif_probe()
1420 sh_mmcif_init_ocr(host); in sh_mmcif_probe()
1431 platform_set_drvdata(pdev, host); in sh_mmcif_probe()
1434 host->power = false; in sh_mmcif_probe()
1436 host->hclk = devm_clk_get(&pdev->dev, NULL); in sh_mmcif_probe()
1437 if (IS_ERR(host->hclk)) { in sh_mmcif_probe()
1438 ret = PTR_ERR(host->hclk); in sh_mmcif_probe()
1442 ret = sh_mmcif_clk_update(host); in sh_mmcif_probe()
1450 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); in sh_mmcif_probe()
1452 sh_mmcif_sync_reset(host); in sh_mmcif_probe()
1453 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_probe()
1457 sh_mmcif_irqt, 0, name, host); in sh_mmcif_probe()
1465 0, "sh_mmc:int", host); in sh_mmcif_probe()
1478 mutex_init(&host->thread_lock); in sh_mmcif_probe()
1487 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, in sh_mmcif_probe()
1488 clk_get_rate(host->hclk) / 1000000UL); in sh_mmcif_probe()
1490 clk_disable_unprepare(host->hclk); in sh_mmcif_probe()
1494 clk_disable_unprepare(host->hclk); in sh_mmcif_probe()
1504 struct sh_mmcif_host *host = platform_get_drvdata(pdev); in sh_mmcif_remove() local
1506 host->dying = true; in sh_mmcif_remove()
1507 clk_prepare_enable(host->hclk); in sh_mmcif_remove()
1512 mmc_remove_host(host->mmc); in sh_mmcif_remove()
1513 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_remove()
1520 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_remove()
1522 clk_disable_unprepare(host->hclk); in sh_mmcif_remove()
1523 mmc_free_host(host->mmc); in sh_mmcif_remove()
1533 struct sh_mmcif_host *host = dev_get_drvdata(dev); in sh_mmcif_suspend() local
1535 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_suspend()