86 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,  in davinci_nand_readl()  function
149 	return davinci_nand_readl(info, NANDF1ECC_OFFSET  in nand_davinci_readecc_1bit()
167 	nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);  in nand_davinci_hwctl_1bit()
247 	val = davinci_nand_readl(info, NANDFCR_OFFSET);  in nand_davinci_hwctl_4bit()
263 	code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;  in nand_davinci_readecc_4bit()
264 	code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;  in nand_davinci_readecc_4bit()
265 	code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;  in nand_davinci_readecc_4bit()
266 	code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;  in nand_davinci_readecc_4bit()
283 		davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);  in nand_davinci_calculate_4bit()
350 	davinci_nand_readl(info, NANDFSR_OFFSET);  in nand_davinci_correct_4bit()
359 	davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);  in nand_davinci_correct_4bit()
366 			davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));  in nand_davinci_correct_4bit()
379 		ecc_state = (davinci_nand_readl(info,  in nand_davinci_correct_4bit()
385 		u32	fsr = davinci_nand_readl(info, NANDFSR_OFFSET);  in nand_davinci_correct_4bit()
389 			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);  in nand_davinci_correct_4bit()
392 			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);  in nand_davinci_correct_4bit()
410 			error_address = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
412 			error_value = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
415 			error_address = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
417 			error_value = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
481 	return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);  in nand_davinci_dev_ready()
757 	val = davinci_nand_readl(info, NANDFCR_OFFSET);  in nand_davinci_probe()
835 	val = davinci_nand_readl(info, NRCSR_OFFSET);  in nand_davinci_probe()