53 #define NDCR		(0x00) /* Control register */  macro
441 	nand_writel(info, NDCR, 0);  in pxa3xx_nand_start()
443 	nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_start()
452 	ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_stop()
454 		ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_stop()
460 		nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_stop()
471 	ndcr = nand_readl(info, NDCR);  in enable_int()
472 	nand_writel(info, NDCR, ndcr & ~int_mask);  in enable_int()
479 	ndcr = nand_readl(info, NDCR);  in disable_int()
480 	nand_writel(info, NDCR, ndcr | int_mask);  in disable_int()
1286 	uint32_t ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_detect_config()