805 	u32 min_clk_period = 0;  in sunxi_nand_chip_set_timings()  local
808 	if (timings->tCLS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
809 		min_clk_period = timings->tCLS_min;  in sunxi_nand_chip_set_timings()
812 	if (timings->tCLH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
813 		min_clk_period = timings->tCLH_min;  in sunxi_nand_chip_set_timings()
816 	if (timings->tCS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
817 		min_clk_period = timings->tCS_min;  in sunxi_nand_chip_set_timings()
820 	if (timings->tCH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
821 		min_clk_period = timings->tCH_min;  in sunxi_nand_chip_set_timings()
824 	if (timings->tWP_min > min_clk_period)  in sunxi_nand_chip_set_timings()
825 		min_clk_period = timings->tWP_min;  in sunxi_nand_chip_set_timings()
828 	if (timings->tWH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
829 		min_clk_period = timings->tWH_min;  in sunxi_nand_chip_set_timings()
832 	if (timings->tALS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
833 		min_clk_period = timings->tALS_min;  in sunxi_nand_chip_set_timings()
836 	if (timings->tDS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
837 		min_clk_period = timings->tDS_min;  in sunxi_nand_chip_set_timings()
840 	if (timings->tDH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
841 		min_clk_period = timings->tDH_min;  in sunxi_nand_chip_set_timings()
844 	if (timings->tRR_min > (min_clk_period * 3))  in sunxi_nand_chip_set_timings()
845 		min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);  in sunxi_nand_chip_set_timings()
848 	if (timings->tALH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
849 		min_clk_period = timings->tALH_min;  in sunxi_nand_chip_set_timings()
852 	if (timings->tRP_min > min_clk_period)  in sunxi_nand_chip_set_timings()
853 		min_clk_period = timings->tRP_min;  in sunxi_nand_chip_set_timings()
856 	if (timings->tREH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
857 		min_clk_period = timings->tREH_min;  in sunxi_nand_chip_set_timings()
860 	if (timings->tRC_min > (min_clk_period * 2))  in sunxi_nand_chip_set_timings()
861 		min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);  in sunxi_nand_chip_set_timings()
864 	if (timings->tWC_min > (min_clk_period * 2))  in sunxi_nand_chip_set_timings()
865 		min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);  in sunxi_nand_chip_set_timings()
869 	min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);  in sunxi_nand_chip_set_timings()
877 	chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;  in sunxi_nand_chip_set_timings()