259 	writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);  in fsl_qspi_unlock_lut()
260 	writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);  in fsl_qspi_unlock_lut()
265 	writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);  in fsl_qspi_lock_lut()
266 	writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);  in fsl_qspi_lock_lut()
276 	writel(reg, q->iobase + QUADSPI_FR);  in fsl_qspi_irq_handler()
297 		writel(0, base + QUADSPI_LUT_BASE + i * 4);  in fsl_qspi_init_lut()
313 	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),  in fsl_qspi_init_lut()
315 	writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),  in fsl_qspi_init_lut()
320 	writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
334 	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),  in fsl_qspi_init_lut()
336 	writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));  in fsl_qspi_init_lut()
340 	writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),  in fsl_qspi_init_lut()
355 	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),  in fsl_qspi_init_lut()
360 	writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),  in fsl_qspi_init_lut()
365 	writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),  in fsl_qspi_init_lut()
370 	writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),  in fsl_qspi_init_lut()
375 	writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),  in fsl_qspi_init_lut()
380 	writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
384 	writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
388 	writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
443 	writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);  in fsl_qspi_runcmd()
444 	writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,  in fsl_qspi_runcmd()
446 	writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);  in fsl_qspi_runcmd()
460 	writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);  in fsl_qspi_runcmd()
474 	writel(reg, base + QUADSPI_MCR);  in fsl_qspi_runcmd()
516 	writel(reg, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalid()
525 	writel(reg, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalid()
540 	writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);  in fsl_qspi_nor_write()
545 		writel(tmp, q->iobase + QUADSPI_TBDR);  in fsl_qspi_nor_write()
563 	writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);  in fsl_qspi_set_map_addr()
564 	writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);  in fsl_qspi_set_map_addr()
565 	writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);  in fsl_qspi_set_map_addr()
566 	writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);  in fsl_qspi_set_map_addr()
588 	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);  in fsl_qspi_init_abh_read()
589 	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);  in fsl_qspi_init_abh_read()
590 	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);  in fsl_qspi_init_abh_read()
595 	writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)  in fsl_qspi_init_abh_read()
599 	writel(0, base + QUADSPI_BUF0IND);  in fsl_qspi_init_abh_read()
600 	writel(0, base + QUADSPI_BUF1IND);  in fsl_qspi_init_abh_read()
601 	writel(0, base + QUADSPI_BUF2IND);  in fsl_qspi_init_abh_read()
605 	writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,  in fsl_qspi_init_abh_read()
625 	writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,  in fsl_qspi_nor_setup()
629 	writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK  in fsl_qspi_nor_setup()
635 	writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,  in fsl_qspi_nor_setup()
639 	writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);  in fsl_qspi_nor_setup()
973 	writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);  in fsl_qspi_remove()
974 	writel(0x0, q->iobase + QUADSPI_RSER);  in fsl_qspi_remove()