Lines Matching refs:reg
117 offset = s->reg + CORE_P_MIB_OFFSET(port); in bcm_sf2_sw_get_ethtool_stats()
143 u32 reg; in bcm_sf2_imp_vlan_setup() local
153 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_imp_vlan_setup()
154 reg |= (1 << cpu_port); in bcm_sf2_imp_vlan_setup()
155 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_imp_vlan_setup()
162 u32 reg, val; in bcm_sf2_imp_setup() local
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_imp_setup()
166 reg &= ~P_TXQ_PSM_VDD(port); in bcm_sf2_imp_setup()
167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_imp_setup()
170 reg = core_readl(priv, CORE_IMP_CTL); in bcm_sf2_imp_setup()
171 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); in bcm_sf2_imp_setup()
172 reg &= ~(RX_DIS | TX_DIS); in bcm_sf2_imp_setup()
173 core_writel(priv, reg, CORE_IMP_CTL); in bcm_sf2_imp_setup()
179 reg = core_readl(priv, CORE_SWITCH_CTRL); in bcm_sf2_imp_setup()
180 reg |= MII_DUMB_FWDG_EN; in bcm_sf2_imp_setup()
181 core_writel(priv, reg, CORE_SWITCH_CTRL); in bcm_sf2_imp_setup()
200 reg = core_readl(priv, CORE_BRCM_HDR_CTRL); in bcm_sf2_imp_setup()
201 reg |= val; in bcm_sf2_imp_setup()
202 core_writel(priv, reg, CORE_BRCM_HDR_CTRL); in bcm_sf2_imp_setup()
207 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS); in bcm_sf2_imp_setup()
208 reg &= ~(1 << port); in bcm_sf2_imp_setup()
209 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS); in bcm_sf2_imp_setup()
214 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS); in bcm_sf2_imp_setup()
215 reg &= ~(1 << port); in bcm_sf2_imp_setup()
216 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS); in bcm_sf2_imp_setup()
219 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP); in bcm_sf2_imp_setup()
220 reg |= (MII_SW_OR | LINK_STS); in bcm_sf2_imp_setup()
221 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP); in bcm_sf2_imp_setup()
227 u32 reg; in bcm_sf2_eee_enable_set() local
229 reg = core_readl(priv, CORE_EEE_EN_CTRL); in bcm_sf2_eee_enable_set()
231 reg |= 1 << port; in bcm_sf2_eee_enable_set()
233 reg &= ~(1 << port); in bcm_sf2_eee_enable_set()
234 core_writel(priv, reg, CORE_EEE_EN_CTRL); in bcm_sf2_eee_enable_set()
240 u32 reg; in bcm_sf2_gphy_enable_set() local
242 reg = reg_readl(priv, REG_SPHY_CNTRL); in bcm_sf2_gphy_enable_set()
244 reg |= PHY_RESET; in bcm_sf2_gphy_enable_set()
245 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS); in bcm_sf2_gphy_enable_set()
246 reg_writel(priv, reg, REG_SPHY_CNTRL); in bcm_sf2_gphy_enable_set()
248 reg = reg_readl(priv, REG_SPHY_CNTRL); in bcm_sf2_gphy_enable_set()
249 reg &= ~PHY_RESET; in bcm_sf2_gphy_enable_set()
251 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; in bcm_sf2_gphy_enable_set()
252 reg_writel(priv, reg, REG_SPHY_CNTRL); in bcm_sf2_gphy_enable_set()
254 reg |= CK25_DIS; in bcm_sf2_gphy_enable_set()
256 reg_writel(priv, reg, REG_SPHY_CNTRL); in bcm_sf2_gphy_enable_set()
260 reg = reg_readl(priv, REG_LED_CNTRL(0)); in bcm_sf2_gphy_enable_set()
261 reg |= SPDLNK_SRC_SEL; in bcm_sf2_gphy_enable_set()
262 reg_writel(priv, reg, REG_LED_CNTRL(0)); in bcm_sf2_gphy_enable_set()
271 u32 reg; in bcm_sf2_port_setup() local
274 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_port_setup()
275 reg &= ~P_TXQ_PSM_VDD(port); in bcm_sf2_port_setup()
276 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_port_setup()
307 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port)); in bcm_sf2_port_setup()
308 reg &= ~PORT_VLAN_CTRL_MASK; in bcm_sf2_port_setup()
309 reg |= (1 << port); in bcm_sf2_port_setup()
310 reg |= priv->port_sts[port].vlan_ctl_mask; in bcm_sf2_port_setup()
311 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port)); in bcm_sf2_port_setup()
326 u32 off, reg; in bcm_sf2_port_disable() local
344 reg = core_readl(priv, off); in bcm_sf2_port_disable()
345 reg |= RX_DIS | TX_DIS; in bcm_sf2_port_disable()
346 core_writel(priv, reg, off); in bcm_sf2_port_disable()
349 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_port_disable()
350 reg |= P_TXQ_PSM_VDD(port); in bcm_sf2_port_disable()
351 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_port_disable()
379 u32 reg; in bcm_sf2_sw_get_eee() local
381 reg = core_readl(priv, CORE_EEE_LPI_INDICATE); in bcm_sf2_sw_get_eee()
383 e->eee_active = !!(reg & (1 << port)); in bcm_sf2_sw_get_eee()
415 u32 reg; in bcm_sf2_sw_fast_age_port() local
419 reg = core_readl(priv, CORE_FAST_AGE_CTRL); in bcm_sf2_sw_fast_age_port()
420 reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE; in bcm_sf2_sw_fast_age_port()
421 core_writel(priv, reg, CORE_FAST_AGE_CTRL); in bcm_sf2_sw_fast_age_port()
424 reg = core_readl(priv, CORE_FAST_AGE_CTRL); in bcm_sf2_sw_fast_age_port()
425 if (!(reg & FAST_AGE_STR_DONE)) in bcm_sf2_sw_fast_age_port()
444 u32 reg, p_ctl; in bcm_sf2_sw_br_join() local
455 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_sw_br_join()
456 reg |= 1 << port; in bcm_sf2_sw_br_join()
457 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_sw_br_join()
458 priv->port_sts[i].vlan_ctl_mask = reg; in bcm_sf2_sw_br_join()
477 u32 reg, p_ctl; in bcm_sf2_sw_br_leave() local
486 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_sw_br_leave()
487 reg &= ~(1 << port); in bcm_sf2_sw_br_leave()
488 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_sw_br_leave()
489 priv->port_sts[port].vlan_ctl_mask = reg; in bcm_sf2_sw_br_leave()
508 u32 reg; in bcm_sf2_sw_br_set_stp_state() local
510 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); in bcm_sf2_sw_br_set_stp_state()
511 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT); in bcm_sf2_sw_br_set_stp_state()
549 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); in bcm_sf2_sw_br_set_stp_state()
550 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT); in bcm_sf2_sw_br_set_stp_state()
551 reg |= hw_state; in bcm_sf2_sw_br_set_stp_state()
552 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); in bcm_sf2_sw_br_set_stp_state()
587 u32 reg; in bcm_sf2_sw_rst() local
589 reg = core_readl(priv, CORE_WATCHDOG_CTRL); in bcm_sf2_sw_rst()
590 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; in bcm_sf2_sw_rst()
591 core_writel(priv, reg, CORE_WATCHDOG_CTRL); in bcm_sf2_sw_rst()
594 reg = core_readl(priv, CORE_WATCHDOG_CTRL); in bcm_sf2_sw_rst()
595 if (!(reg & SOFTWARE_RESET)) in bcm_sf2_sw_rst()
625 u32 reg, rev; in bcm_sf2_sw_setup() local
674 reg = core_readl(priv, CORE_GMNCFGCFG); in bcm_sf2_sw_setup()
675 reg |= RST_MIB_CNT; in bcm_sf2_sw_setup()
676 core_writel(priv, reg, CORE_GMNCFGCFG); in bcm_sf2_sw_setup()
677 reg &= ~RST_MIB_CNT; in bcm_sf2_sw_setup()
678 core_writel(priv, reg, CORE_GMNCFGCFG); in bcm_sf2_sw_setup()
755 u32 reg; in bcm_sf2_sw_indir_rw() local
757 reg = reg_readl(priv, REG_SWITCH_CNTRL); in bcm_sf2_sw_indir_rw()
758 reg |= MDIO_MASTER_SEL; in bcm_sf2_sw_indir_rw()
759 reg_writel(priv, reg, REG_SWITCH_CNTRL); in bcm_sf2_sw_indir_rw()
762 reg = 0x70; in bcm_sf2_sw_indir_rw()
763 reg <<= 2; in bcm_sf2_sw_indir_rw()
764 core_writel(priv, addr, reg); in bcm_sf2_sw_indir_rw()
767 reg = 0x80 << 8 | regnum << 1; in bcm_sf2_sw_indir_rw()
768 reg <<= 2; in bcm_sf2_sw_indir_rw()
771 ret = core_readl(priv, reg); in bcm_sf2_sw_indir_rw()
773 core_writel(priv, val, reg); in bcm_sf2_sw_indir_rw()
775 reg = reg_readl(priv, REG_SWITCH_CNTRL); in bcm_sf2_sw_indir_rw()
776 reg &= ~MDIO_MASTER_SEL; in bcm_sf2_sw_indir_rw()
777 reg_writel(priv, reg, REG_SWITCH_CNTRL); in bcm_sf2_sw_indir_rw()
818 u32 reg; in bcm_sf2_sw_adjust_link() local
844 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); in bcm_sf2_sw_adjust_link()
845 reg &= ~RGMII_MODE_EN; in bcm_sf2_sw_adjust_link()
846 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); in bcm_sf2_sw_adjust_link()
853 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); in bcm_sf2_sw_adjust_link()
854 reg &= ~ID_MODE_DIS; in bcm_sf2_sw_adjust_link()
855 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); in bcm_sf2_sw_adjust_link()
856 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); in bcm_sf2_sw_adjust_link()
858 reg |= port_mode | RGMII_MODE_EN; in bcm_sf2_sw_adjust_link()
860 reg |= ID_MODE_DIS; in bcm_sf2_sw_adjust_link()
864 reg |= TX_PAUSE_EN; in bcm_sf2_sw_adjust_link()
865 reg |= RX_PAUSE_EN; in bcm_sf2_sw_adjust_link()
868 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); in bcm_sf2_sw_adjust_link()
874 reg = SW_OVERRIDE; in bcm_sf2_sw_adjust_link()
877 reg |= SPDSTS_1000 << SPEED_SHIFT; in bcm_sf2_sw_adjust_link()
880 reg |= SPDSTS_100 << SPEED_SHIFT; in bcm_sf2_sw_adjust_link()
885 reg |= LINK_STS; in bcm_sf2_sw_adjust_link()
887 reg |= DUPLX_MODE; in bcm_sf2_sw_adjust_link()
889 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port)); in bcm_sf2_sw_adjust_link()
897 u32 reg; in bcm_sf2_sw_fixed_link_update() local
920 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port)); in bcm_sf2_sw_fixed_link_update()
921 reg |= SW_OVERRIDE; in bcm_sf2_sw_fixed_link_update()
923 reg |= LINK_STS; in bcm_sf2_sw_fixed_link_update()
925 reg &= ~LINK_STS; in bcm_sf2_sw_fixed_link_update()
926 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port)); in bcm_sf2_sw_fixed_link_update()