Lines Matching refs:x
45 #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_BASE + \ argument
46 ((x) * REG_RGMII_CNTRL_SIZE))
65 #define REG_LED_CNTRL(x) (REG_LED_CNTRL_BASE + (x) * 4) argument
77 #define P_LINK_UP_IRQ(x) (1 << (0 + (x))) argument
78 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x))) argument
79 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x))) argument
80 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x))) argument
81 #define P_GPHY_IRQ(x) (1 << (4 + (x))) argument
83 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \ argument
84 P_LINK_DOWN_IRQ((x)) | \
85 P_ENERGY_ON_IRQ((x)) | \
86 P_ENERGY_OFF_IRQ((x)) | \
87 P_GPHY_IRQ((x)))
107 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ) argument
111 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4)) argument
150 #define SW_LEARN_CNTL(x) (1 << (x)) argument
152 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4) argument
237 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ argument
238 ((x) * P_TXQ_PSM_VDD_SHIFT))
242 #define CORE_P_MIB_OFFSET(x) (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE) argument
244 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) argument