48 	u32 val;  in alx_wait_mdio_idle()  local
52 		val = alx_read_mem32(hw, ALX_MDIO);  in alx_wait_mdio_idle()
53 		if (!(val & ALX_MDIO_BUSY))  in alx_wait_mdio_idle()
64 	u32 val, clk_sel;  in alx_read_phy_core()  local
75 		val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT |  in alx_read_phy_core()
77 		alx_write_mem32(hw, ALX_MDIO_EXTN, val);  in alx_read_phy_core()
79 		val = ALX_MDIO_SPRES_PRMBL | ALX_MDIO_START |  in alx_read_phy_core()
83 		val = ALX_MDIO_SPRES_PRMBL |  in alx_read_phy_core()
88 	alx_write_mem32(hw, ALX_MDIO, val);  in alx_read_phy_core()
93 	val = alx_read_mem32(hw, ALX_MDIO);  in alx_read_phy_core()
94 	*phy_data = ALX_GET_FIELD(val, ALX_MDIO_DATA);  in alx_read_phy_core()
101 	u32 val, clk_sel;  in alx_write_phy_core()  local
109 		val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT |  in alx_write_phy_core()
111 		alx_write_mem32(hw, ALX_MDIO_EXTN, val);  in alx_write_phy_core()
113 		val = ALX_MDIO_SPRES_PRMBL |  in alx_write_phy_core()
118 		val = ALX_MDIO_SPRES_PRMBL |  in alx_write_phy_core()
124 	alx_write_mem32(hw, ALX_MDIO, val);  in alx_write_phy_core()
239 	u32 val;  in alx_get_phy_config()  local
242 	val = alx_read_mem32(hw, ALX_PHY_CTRL);  in alx_get_phy_config()
244 	if ((val & ALX_PHY_CTRL_DSPRST_OUT) == 0)  in alx_get_phy_config()
247 	val = alx_read_mem32(hw, ALX_DRV);  in alx_get_phy_config()
248 	val = ALX_GET_FIELD(val, ALX_DRV_PHY);  in alx_get_phy_config()
249 	if (ALX_DRV_PHY_UNKNOWN == val)  in alx_get_phy_config()
254 		return val;  in alx_get_phy_config()
259 static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val)  in alx_wait_reg()  argument
267 			if (val)  in alx_wait_reg()
268 				*val = read;  in alx_wait_reg()
293 	u32 val;  in alx_get_perm_macaddr()  local
300 	if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val))  in alx_get_perm_macaddr()
302 	alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START);  in alx_get_perm_macaddr()
309 	val = alx_read_mem32(hw, ALX_EFLD);  in alx_get_perm_macaddr()
310 	if (val & (ALX_EFLD_F_EXIST | ALX_EFLD_E_EXIST)) {  in alx_get_perm_macaddr()
312 				  ALX_EFLD_STAT | ALX_EFLD_START, &val))  in alx_get_perm_macaddr()
314 		alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START);  in alx_get_perm_macaddr()
326 	u32 val;  in alx_set_macaddr()  local
329 	val = be32_to_cpu(get_unaligned((__be32 *)(addr + 2)));  in alx_set_macaddr()
330 	alx_write_mem32(hw, ALX_STAD0, val);  in alx_set_macaddr()
331 	val = be16_to_cpu(get_unaligned((__be16 *)addr));  in alx_set_macaddr()
332 	alx_write_mem32(hw, ALX_STAD1, val);  in alx_set_macaddr()
337 	u32 val, val2;  in alx_reset_osc()  local
340 	val = alx_read_mem32(hw, ALX_MISC3);  in alx_reset_osc()
342 			(val & ~ALX_MISC3_25M_BY_SW) |  in alx_reset_osc()
348 	val = alx_read_mem32(hw, ALX_MISC);  in alx_reset_osc()
353 		ALX_SET_FIELD(val, ALX_MISC_PSW_OCP, ALX_MISC_PSW_OCP_DEF);  in alx_reset_osc()
355 		val &= ~ALX_MISC_INTNLOSC_OPEN;  in alx_reset_osc()
356 		alx_write_mem32(hw, ALX_MISC, val);  in alx_reset_osc()
357 		alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);  in alx_reset_osc()
364 		val &= ~ALX_MISC_INTNLOSC_OPEN;  in alx_reset_osc()
367 			val &= ~ALX_MISC_ISO_EN;  in alx_reset_osc()
369 		alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);  in alx_reset_osc()
370 		alx_write_mem32(hw, ALX_MISC, val);  in alx_reset_osc()
378 	u32 rxq, txq, val;  in alx_stop_mac()  local
392 		val = alx_read_mem32(hw, ALX_MAC_STS);  in alx_stop_mac()
393 		if (!(val & ALX_MAC_STS_IDLE))  in alx_stop_mac()
403 	u32 val, pmctrl;  in alx_reset_mac()  local
434 	val = alx_read_mem32(hw, ALX_MASTER);  in alx_reset_mac()
436 			val | ALX_MASTER_DMA_MAC_RST | ALX_MASTER_OOB_DIS);  in alx_reset_mac()
441 		val = alx_read_mem32(hw, ALX_RFD_PIDX);  in alx_reset_mac()
442 		if (val == 0)  in alx_reset_mac()
447 		val = alx_read_mem32(hw, ALX_MASTER);  in alx_reset_mac()
448 		if ((val & ALX_MASTER_DMA_MAC_RST) == 0)  in alx_reset_mac()
457 		alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS);  in alx_reset_mac()
468 	val = alx_read_mem32(hw, ALX_MISC3);  in alx_reset_mac()
470 			(val & ~ALX_MISC3_25M_BY_SW) |  in alx_reset_mac()
472 	val = alx_read_mem32(hw, ALX_MISC);  in alx_reset_mac()
473 	val &= ~ALX_MISC_INTNLOSC_OPEN;  in alx_reset_mac()
475 		val &= ~ALX_MISC_ISO_EN;  in alx_reset_mac()
476 	alx_write_mem32(hw, ALX_MISC, val);  in alx_reset_mac()
482 	val = alx_read_mem32(hw, ALX_SERDES);  in alx_reset_mac()
484 			val | ALX_SERDES_MACCLK_SLWDWN |  in alx_reset_mac()
493 	u32 val;  in alx_reset_phy()  local
497 	val = alx_read_mem32(hw, ALX_PHY_CTRL);  in alx_reset_phy()
498 	val &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_IDDQ |  in alx_reset_phy()
501 	val |= ALX_PHY_CTRL_RST_ANALOG;  in alx_reset_phy()
503 	val |= (ALX_PHY_CTRL_HIB_PULSE | ALX_PHY_CTRL_HIB_EN);  in alx_reset_phy()
504 	alx_write_mem32(hw, ALX_PHY_CTRL, val);  in alx_reset_phy()
506 	alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT);  in alx_reset_phy()
519 	val = alx_read_mem32(hw, ALX_LPI_CTRL);  in alx_reset_phy()
520 	alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN);  in alx_reset_phy()
563 	u32 val;  in alx_reset_pcie()  local
574 	val = alx_read_mem32(hw, ALX_WOL0);  in alx_reset_pcie()
577 	val = alx_read_mem32(hw, ALX_PDLL_TRNS1);  in alx_reset_pcie()
578 	alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN);  in alx_reset_pcie()
581 	val = alx_read_mem32(hw, ALX_UE_SVRT);  in alx_reset_pcie()
582 	val &= ~(ALX_UE_SVRT_DLPROTERR | ALX_UE_SVRT_FCPROTERR);  in alx_reset_pcie()
583 	alx_write_mem32(hw, ALX_UE_SVRT, val);  in alx_reset_pcie()
586 	val = alx_read_mem32(hw, ALX_MASTER);  in alx_reset_pcie()
588 		if ((val & ALX_MASTER_WAKEN_25M) == 0 ||  in alx_reset_pcie()
589 		    (val & ALX_MASTER_PCLKSEL_SRDS) == 0)  in alx_reset_pcie()
591 					val | ALX_MASTER_PCLKSEL_SRDS |  in alx_reset_pcie()
594 		if ((val & ALX_MASTER_WAKEN_25M) == 0 ||  in alx_reset_pcie()
595 		    (val & ALX_MASTER_PCLKSEL_SRDS) != 0)  in alx_reset_pcie()
597 					(val & ~ALX_MASTER_PCLKSEL_SRDS) |  in alx_reset_pcie()
725 	u32 val;  in alx_setup_speed_duplex()  local
729 	val = alx_read_mem32(hw, ALX_DRV);  in alx_setup_speed_duplex()
730 	ALX_SET_FIELD(val, ALX_DRV_PHY, 0);  in alx_setup_speed_duplex()
769 		val |= ethadv_to_hw_cfg(hw, ethadv);  in alx_setup_speed_duplex()
772 	alx_write_mem32(hw, ALX_DRV, val);  in alx_setup_speed_duplex()
933 	u32 val, raw_mtu, max_payload;  in alx_configure_basic()  local
948 	val = alx_read_mem32(hw, ALX_MASTER);  in alx_configure_basic()
949 	val |= ALX_MASTER_IRQMOD2_EN |  in alx_configure_basic()
952 	alx_write_mem32(hw, ALX_MASTER, val);  in alx_configure_basic()
967 		val = (raw_mtu + 8 + 7) >> 3;  in alx_configure_basic()
969 		val = ALX_TXQ1_JUMBO_TSO_TH >> 3;  in alx_configure_basic()
970 	alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN);  in alx_configure_basic()
980 	val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_TXQ0_TPD_BURSTPREF_SHIFT |  in alx_configure_basic()
984 	alx_write_mem32(hw, ALX_TXQ0, val);  in alx_configure_basic()
985 	val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q1_NUMPREF_SHIFT |  in alx_configure_basic()
989 	alx_write_mem32(hw, ALX_HQTPD, val);  in alx_configure_basic()
992 	val = alx_read_mem32(hw, ALX_SRAM5);  in alx_configure_basic()
993 	val = ALX_GET_FIELD(val, ALX_SRAM_RXF_LEN) << 3;  in alx_configure_basic()
994 	if (val > ALX_SRAM_RXF_LEN_8K) {  in alx_configure_basic()
996 		val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3;  in alx_configure_basic()
999 		val = (val - ALX_MTU_STD_ALGN) >> 3;  in alx_configure_basic()
1003 			val << ALX_RXQ2_RXF_XON_THRESH_SHIFT);  in alx_configure_basic()
1004 	val = ALX_RXQ0_NUM_RFD_PREF_DEF << ALX_RXQ0_NUM_RFD_PREF_SHIFT |  in alx_configure_basic()
1011 		ALX_SET_FIELD(val, ALX_RXQ0_ASPM_THRESH,  in alx_configure_basic()
1014 	alx_write_mem32(hw, ALX_RXQ0, val);  in alx_configure_basic()
1016 	val = alx_read_mem32(hw, ALX_DMA);  in alx_configure_basic()
1017 	val = ALX_DMA_RORDER_MODE_OUT << ALX_DMA_RORDER_MODE_SHIFT |  in alx_configure_basic()
1023 	alx_write_mem32(hw, ALX_DMA, val);  in alx_configure_basic()
1026 	val = ALX_WRR_PRI_RESTRICT_NONE << ALX_WRR_PRI_SHIFT |  in alx_configure_basic()
1031 	alx_write_mem32(hw, ALX_WRR, val);  in alx_configure_basic()