64 		val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);  in bgmac_dma_tx_reset()
87 		val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);  in bgmac_dma_tx_reset()
99 	ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);  in bgmac_dma_tx_enable()
249 	empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);  in bgmac_dma_tx_free()
316 	ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);  in bgmac_dma_rx_enable()
420 	end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);  in bgmac_dma_rx_read()
503 		if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))  in bgmac_dma_unaligned()
509 		if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))  in bgmac_dma_unaligned()
807 	if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)  in bgmac_phy_write()
886 	u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);  in bgmac_cmdcfg_maskset()
927 				bgmac_read(bgmac,
931 				bgmac_read(bgmac,
948 		bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));  in bgmac_clear_mib()
950 		bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));  in bgmac_clear_mib()
997 		imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &  in bgmac_miiconfig()
1146 	bgmac_read(bgmac, BGMAC_INT_MASK);  in bgmac_chip_intrs_off()
1160 	cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);  in bgmac_enable()
1167 	mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>  in bgmac_enable()
1193 		rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);  in bgmac_enable()
1232 	u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);  in bgmac_interrupt()
1262 	if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))  in bgmac_poll()