249 static void bnx2_init_napi(struct bnx2 *bp);
250 static void bnx2_del_napi(struct bnx2 *bp);
252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)  in bnx2_tx_avail()  argument
268 	return bp->tx_ring_size - diff;  in bnx2_tx_avail()
272 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)  in bnx2_reg_rd_ind()  argument
276 	spin_lock_bh(&bp->indirect_lock);  in bnx2_reg_rd_ind()
277 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
278 	val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);  in bnx2_reg_rd_ind()
279 	spin_unlock_bh(&bp->indirect_lock);  in bnx2_reg_rd_ind()
284 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_reg_wr_ind()  argument
286 	spin_lock_bh(&bp->indirect_lock);  in bnx2_reg_wr_ind()
287 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
288 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
289 	spin_unlock_bh(&bp->indirect_lock);  in bnx2_reg_wr_ind()
293 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_shmem_wr()  argument
295 	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);  in bnx2_shmem_wr()
299 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)  in bnx2_shmem_rd()  argument
301 	return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);  in bnx2_shmem_rd()
305 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)  in bnx2_ctx_wr()  argument
308 	spin_lock_bh(&bp->indirect_lock);  in bnx2_ctx_wr()
309 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_ctx_wr()
312 		BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
313 		BNX2_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
316 			val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);  in bnx2_ctx_wr()
322 		BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
323 		BNX2_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
325 	spin_unlock_bh(&bp->indirect_lock);  in bnx2_ctx_wr()
332 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_drv_ctl()  local
337 		bnx2_reg_wr_ind(bp, io->offset, io->data);  in bnx2_drv_ctl()
340 		io->data = bnx2_reg_rd_ind(bp, io->offset);  in bnx2_drv_ctl()
343 		bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);  in bnx2_drv_ctl()
351 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)  in bnx2_setup_cnic_irq_info()  argument
353 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_setup_cnic_irq_info()
354 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_setup_cnic_irq_info()
357 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_setup_cnic_irq_info()
360 		sb_id = bp->irq_nvecs;  in bnx2_setup_cnic_irq_info()
370 	cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;  in bnx2_setup_cnic_irq_info()
381 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_register_cnic()  local
382 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_register_cnic()
390 	if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))  in bnx2_register_cnic()
393 	bp->cnic_data = data;  in bnx2_register_cnic()
394 	rcu_assign_pointer(bp->cnic_ops, ops);  in bnx2_register_cnic()
399 	bnx2_setup_cnic_irq_info(bp);  in bnx2_register_cnic()
406 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_unregister_cnic()  local
407 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_unregister_cnic()
408 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_unregister_cnic()
410 	mutex_lock(&bp->cnic_lock);  in bnx2_unregister_cnic()
413 	RCU_INIT_POINTER(bp->cnic_ops, NULL);  in bnx2_unregister_cnic()
414 	mutex_unlock(&bp->cnic_lock);  in bnx2_unregister_cnic()
421 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_cnic_probe()  local
422 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_cnic_probe()
428 	cp->chip_id = bp->chip_id;  in bnx2_cnic_probe()
429 	cp->pdev = bp->pdev;  in bnx2_cnic_probe()
430 	cp->io_base = bp->regview;  in bnx2_cnic_probe()
439 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
444 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_stop()
445 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_stop()
446 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_stop()
449 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_stop()
451 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_stop()
455 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
460 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_start()
461 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_start()
462 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_start()
464 		if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_cnic_start()
465 			struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_cnic_start()
470 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_start()
472 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_start()
478 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
483 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
490 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)  in bnx2_read_phy()  argument
495 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
496 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
499 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
500 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
505 	val1 = (bp->phy_addr << 21) | (reg << 16) |  in bnx2_read_phy()
508 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
513 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
517 			val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
533 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
534 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
537 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
538 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
547 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)  in bnx2_write_phy()  argument
552 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
553 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
556 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
557 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
562 	val1 = (bp->phy_addr << 21) | (reg << 16) | val |  in bnx2_write_phy()
565 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
570 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_write_phy()
582 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
583 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
586 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
587 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
596 bnx2_disable_int(struct bnx2 *bp)  in bnx2_disable_int()  argument
601 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_disable_int()
602 		bnapi = &bp->bnx2_napi[i];  in bnx2_disable_int()
603 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
606 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_disable_int()
610 bnx2_enable_int(struct bnx2 *bp)  in bnx2_enable_int()  argument
615 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_enable_int()
616 		bnapi = &bp->bnx2_napi[i];  in bnx2_enable_int()
618 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
623 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
627 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
631 bnx2_disable_int_sync(struct bnx2 *bp)  in bnx2_disable_int_sync()  argument
635 	atomic_inc(&bp->intr_sem);  in bnx2_disable_int_sync()
636 	if (!netif_running(bp->dev))  in bnx2_disable_int_sync()
639 	bnx2_disable_int(bp);  in bnx2_disable_int_sync()
640 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_disable_int_sync()
641 		synchronize_irq(bp->irq_tbl[i].vector);  in bnx2_disable_int_sync()
645 bnx2_napi_disable(struct bnx2 *bp)  in bnx2_napi_disable()  argument
649 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_disable()
650 		napi_disable(&bp->bnx2_napi[i].napi);  in bnx2_napi_disable()
654 bnx2_napi_enable(struct bnx2 *bp)  in bnx2_napi_enable()  argument
658 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_enable()
659 		napi_enable(&bp->bnx2_napi[i].napi);  in bnx2_napi_enable()
663 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)  in bnx2_netif_stop()  argument
666 		bnx2_cnic_stop(bp);  in bnx2_netif_stop()
667 	if (netif_running(bp->dev)) {  in bnx2_netif_stop()
668 		bnx2_napi_disable(bp);  in bnx2_netif_stop()
669 		netif_tx_disable(bp->dev);  in bnx2_netif_stop()
671 	bnx2_disable_int_sync(bp);  in bnx2_netif_stop()
672 	netif_carrier_off(bp->dev);	/* prevent tx timeout */  in bnx2_netif_stop()
676 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)  in bnx2_netif_start()  argument
678 	if (atomic_dec_and_test(&bp->intr_sem)) {  in bnx2_netif_start()
679 		if (netif_running(bp->dev)) {  in bnx2_netif_start()
680 			netif_tx_wake_all_queues(bp->dev);  in bnx2_netif_start()
681 			spin_lock_bh(&bp->phy_lock);  in bnx2_netif_start()
682 			if (bp->link_up)  in bnx2_netif_start()
683 				netif_carrier_on(bp->dev);  in bnx2_netif_start()
684 			spin_unlock_bh(&bp->phy_lock);  in bnx2_netif_start()
685 			bnx2_napi_enable(bp);  in bnx2_netif_start()
686 			bnx2_enable_int(bp);  in bnx2_netif_start()
688 				bnx2_cnic_start(bp);  in bnx2_netif_start()
694 bnx2_free_tx_mem(struct bnx2 *bp)  in bnx2_free_tx_mem()  argument
698 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_mem()
699 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_mem()
703 			dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_free_tx_mem()
714 bnx2_free_rx_mem(struct bnx2 *bp)  in bnx2_free_rx_mem()  argument
718 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_mem()
719 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_mem()
723 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_free_rx_mem()
725 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
733 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_free_rx_mem()
735 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
746 bnx2_alloc_tx_mem(struct bnx2 *bp)  in bnx2_alloc_tx_mem()  argument
750 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_alloc_tx_mem()
751 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_tx_mem()
759 			dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_alloc_tx_mem()
768 bnx2_alloc_rx_mem(struct bnx2 *bp)  in bnx2_alloc_rx_mem()  argument
772 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_alloc_rx_mem()
773 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_rx_mem()
778 			vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);  in bnx2_alloc_rx_mem()
782 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_alloc_rx_mem()
784 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
793 		if (bp->rx_pg_ring_size) {  in bnx2_alloc_rx_mem()
795 						  bp->rx_max_pg_ring);  in bnx2_alloc_rx_mem()
801 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_alloc_rx_mem()
803 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
816 bnx2_free_mem(struct bnx2 *bp)  in bnx2_free_mem()  argument
819 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_free_mem()
821 	bnx2_free_tx_mem(bp);  in bnx2_free_mem()
822 	bnx2_free_rx_mem(bp);  in bnx2_free_mem()
824 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_free_mem()
825 		if (bp->ctx_blk[i]) {  in bnx2_free_mem()
826 			dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,  in bnx2_free_mem()
827 					  bp->ctx_blk[i],  in bnx2_free_mem()
828 					  bp->ctx_blk_mapping[i]);  in bnx2_free_mem()
829 			bp->ctx_blk[i] = NULL;  in bnx2_free_mem()
833 		dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_free_mem()
835 				  bp->status_blk_mapping);  in bnx2_free_mem()
837 		bp->stats_blk = NULL;  in bnx2_free_mem()
842 bnx2_alloc_mem(struct bnx2 *bp)  in bnx2_alloc_mem()  argument
850 	if (bp->flags & BNX2_FLAG_MSIX_CAP)  in bnx2_alloc_mem()
853 	bp->status_stats_size = status_blk_size +  in bnx2_alloc_mem()
856 	status_blk = dma_zalloc_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_alloc_mem()
857 					 &bp->status_blk_mapping, GFP_KERNEL);  in bnx2_alloc_mem()
861 	bnapi = &bp->bnx2_napi[0];  in bnx2_alloc_mem()
867 	if (bp->flags & BNX2_FLAG_MSIX_CAP) {  in bnx2_alloc_mem()
868 		for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_alloc_mem()
871 			bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_mem()
883 	bp->stats_blk = status_blk + status_blk_size;  in bnx2_alloc_mem()
885 	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;  in bnx2_alloc_mem()
887 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_alloc_mem()
888 		bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;  in bnx2_alloc_mem()
889 		if (bp->ctx_pages == 0)  in bnx2_alloc_mem()
890 			bp->ctx_pages = 1;  in bnx2_alloc_mem()
891 		for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_alloc_mem()
892 			bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_mem()
894 						&bp->ctx_blk_mapping[i],  in bnx2_alloc_mem()
896 			if (bp->ctx_blk[i] == NULL)  in bnx2_alloc_mem()
901 	err = bnx2_alloc_rx_mem(bp);  in bnx2_alloc_mem()
905 	err = bnx2_alloc_tx_mem(bp);  in bnx2_alloc_mem()
912 	bnx2_free_mem(bp);  in bnx2_alloc_mem()
917 bnx2_report_fw_link(struct bnx2 *bp)  in bnx2_report_fw_link()  argument
921 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_report_fw_link()
924 	if (bp->link_up) {  in bnx2_report_fw_link()
927 		switch (bp->line_speed) {  in bnx2_report_fw_link()
929 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
935 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
941 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
947 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
956 		if (bp->autoneg) {  in bnx2_report_fw_link()
959 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
960 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
963 			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)  in bnx2_report_fw_link()
972 	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);  in bnx2_report_fw_link()
976 bnx2_xceiver_str(struct bnx2 *bp)  in bnx2_xceiver_str()  argument
978 	return (bp->phy_port == PORT_FIBRE) ? "SerDes" :  in bnx2_xceiver_str()
979 		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :  in bnx2_xceiver_str()
984 bnx2_report_link(struct bnx2 *bp)  in bnx2_report_link()  argument
986 	if (bp->link_up) {  in bnx2_report_link()
987 		netif_carrier_on(bp->dev);  in bnx2_report_link()
988 		netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",  in bnx2_report_link()
989 			    bnx2_xceiver_str(bp),  in bnx2_report_link()
990 			    bp->line_speed,  in bnx2_report_link()
991 			    bp->duplex == DUPLEX_FULL ? "full" : "half");  in bnx2_report_link()
993 		if (bp->flow_ctrl) {  in bnx2_report_link()
994 			if (bp->flow_ctrl & FLOW_CTRL_RX) {  in bnx2_report_link()
996 				if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_report_link()
1006 		netif_carrier_off(bp->dev);  in bnx2_report_link()
1007 		netdev_err(bp->dev, "NIC %s Link is Down\n",  in bnx2_report_link()
1008 			   bnx2_xceiver_str(bp));  in bnx2_report_link()
1011 	bnx2_report_fw_link(bp);  in bnx2_report_link()
1015 bnx2_resolve_flow_ctrl(struct bnx2 *bp)  in bnx2_resolve_flow_ctrl()  argument
1019 	bp->flow_ctrl = 0;  in bnx2_resolve_flow_ctrl()
1020 	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_resolve_flow_ctrl()
1023 		if (bp->duplex == DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1024 			bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_resolve_flow_ctrl()
1029 	if (bp->duplex != DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1033 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_resolve_flow_ctrl()
1034 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_resolve_flow_ctrl()
1037 		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_resolve_flow_ctrl()
1039 			bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1041 			bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1045 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_resolve_flow_ctrl()
1046 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_resolve_flow_ctrl()
1048 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_resolve_flow_ctrl()
1069 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1072 				bp->flow_ctrl = FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1077 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1085 			bp->flow_ctrl = FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1091 bnx2_5709s_linkup(struct bnx2 *bp)  in bnx2_5709s_linkup()  argument
1095 	bp->link_up = 1;  in bnx2_5709s_linkup()
1097 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);  in bnx2_5709s_linkup()
1098 	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);  in bnx2_5709s_linkup()
1099 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_5709s_linkup()
1101 	if ((bp->autoneg & AUTONEG_SPEED) == 0) {  in bnx2_5709s_linkup()
1102 		bp->line_speed = bp->req_line_speed;  in bnx2_5709s_linkup()
1103 		bp->duplex = bp->req_duplex;  in bnx2_5709s_linkup()
1109 			bp->line_speed = SPEED_10;  in bnx2_5709s_linkup()
1112 			bp->line_speed = SPEED_100;  in bnx2_5709s_linkup()
1116 			bp->line_speed = SPEED_1000;  in bnx2_5709s_linkup()
1119 			bp->line_speed = SPEED_2500;  in bnx2_5709s_linkup()
1123 		bp->duplex = DUPLEX_FULL;  in bnx2_5709s_linkup()
1125 		bp->duplex = DUPLEX_HALF;  in bnx2_5709s_linkup()
1130 bnx2_5708s_linkup(struct bnx2 *bp)  in bnx2_5708s_linkup()  argument
1134 	bp->link_up = 1;  in bnx2_5708s_linkup()
1135 	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_5708s_linkup()
1138 			bp->line_speed = SPEED_10;  in bnx2_5708s_linkup()
1141 			bp->line_speed = SPEED_100;  in bnx2_5708s_linkup()
1144 			bp->line_speed = SPEED_1000;  in bnx2_5708s_linkup()
1147 			bp->line_speed = SPEED_2500;  in bnx2_5708s_linkup()
1151 		bp->duplex = DUPLEX_FULL;  in bnx2_5708s_linkup()
1153 		bp->duplex = DUPLEX_HALF;  in bnx2_5708s_linkup()
1159 bnx2_5706s_linkup(struct bnx2 *bp)  in bnx2_5706s_linkup()  argument
1163 	bp->link_up = 1;  in bnx2_5706s_linkup()
1164 	bp->line_speed = SPEED_1000;  in bnx2_5706s_linkup()
1166 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706s_linkup()
1168 		bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1171 		bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1178 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_5706s_linkup()
1179 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_5706s_linkup()
1185 			bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1188 			bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1196 bnx2_copper_linkup(struct bnx2 *bp)  in bnx2_copper_linkup()  argument
1200 	bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1202 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_copper_linkup()
1206 		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);  in bnx2_copper_linkup()
1207 		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);  in bnx2_copper_linkup()
1211 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1212 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1215 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1216 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1219 			bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_copper_linkup()
1220 			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_copper_linkup()
1224 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1225 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1228 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1229 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1232 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1233 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1236 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1237 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1240 				bp->line_speed = 0;  in bnx2_copper_linkup()
1241 				bp->link_up = 0;  in bnx2_copper_linkup()
1247 			bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1250 			bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1253 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1256 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1260 	if (bp->link_up) {  in bnx2_copper_linkup()
1263 		bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);  in bnx2_copper_linkup()
1265 			bp->phy_flags |= BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1272 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)  in bnx2_init_rx_context()  argument
1280 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_init_rx_context()
1283 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);  in bnx2_init_rx_context()
1287 bnx2_init_all_rx_contexts(struct bnx2 *bp)  in bnx2_init_all_rx_contexts()  argument
1292 	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {  in bnx2_init_all_rx_contexts()
1295 		bnx2_init_rx_context(bp, cid);  in bnx2_init_all_rx_contexts()
1300 bnx2_set_mac_link(struct bnx2 *bp)  in bnx2_set_mac_link()  argument
1304 	BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1305 	if (bp->link_up && (bp->line_speed == SPEED_1000) &&  in bnx2_set_mac_link()
1306 		(bp->duplex == DUPLEX_HALF)) {  in bnx2_set_mac_link()
1307 		BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1311 	val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_link()
1317 	if (bp->link_up) {  in bnx2_set_mac_link()
1318 		switch (bp->line_speed) {  in bnx2_set_mac_link()
1320 				if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {  in bnx2_set_mac_link()
1341 	if (bp->duplex == DUPLEX_HALF)  in bnx2_set_mac_link()
1343 	BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1346 	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1348 	if (bp->flow_ctrl & FLOW_CTRL_RX)  in bnx2_set_mac_link()
1349 		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1350 	BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1353 	val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);  in bnx2_set_mac_link()
1356 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_set_mac_link()
1358 	BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1361 	BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1363 	bnx2_init_all_rx_contexts(bp);  in bnx2_set_mac_link()
1367 bnx2_enable_bmsr1(struct bnx2 *bp)  in bnx2_enable_bmsr1()  argument
1369 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_enable_bmsr1()
1370 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_enable_bmsr1()
1371 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_bmsr1()
1376 bnx2_disable_bmsr1(struct bnx2 *bp)  in bnx2_disable_bmsr1()  argument
1378 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_disable_bmsr1()
1379 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_disable_bmsr1()
1380 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_bmsr1()
1385 bnx2_test_and_enable_2g5(struct bnx2 *bp)  in bnx2_test_and_enable_2g5()  argument
1390 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_enable_2g5()
1393 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_test_and_enable_2g5()
1394 		bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_test_and_enable_2g5()
1396 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1397 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_enable_2g5()
1399 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_enable_2g5()
1402 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_enable_2g5()
1406 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1407 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_enable_2g5()
1414 bnx2_test_and_disable_2g5(struct bnx2 *bp)  in bnx2_test_and_disable_2g5()  argument
1419 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_disable_2g5()
1422 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1423 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_disable_2g5()
1425 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_disable_2g5()
1428 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_disable_2g5()
1432 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1433 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_disable_2g5()
1440 bnx2_enable_forced_2g5(struct bnx2 *bp)  in bnx2_enable_forced_2g5()  argument
1445 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_enable_forced_2g5()
1448 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_enable_forced_2g5()
1451 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1453 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_enable_forced_2g5()
1457 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_enable_forced_2g5()
1460 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1462 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1464 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_enable_forced_2g5()
1465 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1475 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_enable_forced_2g5()
1477 		if (bp->req_duplex == DUPLEX_FULL)  in bnx2_enable_forced_2g5()
1480 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_enable_forced_2g5()
1484 bnx2_disable_forced_2g5(struct bnx2 *bp)  in bnx2_disable_forced_2g5()  argument
1489 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_disable_forced_2g5()
1492 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_disable_forced_2g5()
1495 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1497 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_disable_forced_2g5()
1499 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_disable_forced_2g5()
1502 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1504 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1506 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_disable_forced_2g5()
1507 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1517 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_disable_forced_2g5()
1519 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_disable_forced_2g5()
1523 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)  in bnx2_5706s_force_link_dn()  argument
1527 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);  in bnx2_5706s_force_link_dn()
1528 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_5706s_force_link_dn()
1530 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);  in bnx2_5706s_force_link_dn()
1532 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);  in bnx2_5706s_force_link_dn()
1536 bnx2_set_link(struct bnx2 *bp)  in bnx2_set_link()  argument
1541 	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {  in bnx2_set_link()
1542 		bp->link_up = 1;  in bnx2_set_link()
1546 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_set_link()
1549 	link_up = bp->link_up;  in bnx2_set_link()
1551 	bnx2_enable_bmsr1(bp);  in bnx2_set_link()
1552 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1553 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1554 	bnx2_disable_bmsr1(bp);  in bnx2_set_link()
1556 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1557 	    (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {  in bnx2_set_link()
1560 		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {  in bnx2_set_link()
1561 			bnx2_5706s_force_link_dn(bp, 0);  in bnx2_set_link()
1562 			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_set_link()
1564 		val = BNX2_RD(bp, BNX2_EMAC_STATUS);  in bnx2_set_link()
1566 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_set_link()
1567 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1568 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1578 		bp->link_up = 1;  in bnx2_set_link()
1580 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_link()
1581 			if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_set_link()
1582 				bnx2_5706s_linkup(bp);  in bnx2_set_link()
1583 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_set_link()
1584 				bnx2_5708s_linkup(bp);  in bnx2_set_link()
1585 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_set_link()
1586 				bnx2_5709s_linkup(bp);  in bnx2_set_link()
1589 			bnx2_copper_linkup(bp);  in bnx2_set_link()
1591 		bnx2_resolve_flow_ctrl(bp);  in bnx2_set_link()
1594 		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1595 		    (bp->autoneg & AUTONEG_SPEED))  in bnx2_set_link()
1596 			bnx2_disable_forced_2g5(bp);  in bnx2_set_link()
1598 		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {  in bnx2_set_link()
1601 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_set_link()
1603 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_set_link()
1605 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_set_link()
1607 		bp->link_up = 0;  in bnx2_set_link()
1610 	if (bp->link_up != link_up) {  in bnx2_set_link()
1611 		bnx2_report_link(bp);  in bnx2_set_link()
1614 	bnx2_set_mac_link(bp);  in bnx2_set_link()
1620 bnx2_reset_phy(struct bnx2 *bp)  in bnx2_reset_phy()  argument
1625         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);  in bnx2_reset_phy()
1631 		bnx2_read_phy(bp, bp->mii_bmcr, &reg);  in bnx2_reset_phy()
1644 bnx2_phy_get_pause_adv(struct bnx2 *bp)  in bnx2_phy_get_pause_adv()  argument
1648 	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==  in bnx2_phy_get_pause_adv()
1651 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1658 	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {  in bnx2_phy_get_pause_adv()
1659 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1666 	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {  in bnx2_phy_get_pause_adv()
1667 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1680 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_remote_phy()  argument
1681 __releases(&bp->phy_lock)  in bnx2_setup_remote_phy()
1682 __acquires(&bp->phy_lock)  in bnx2_setup_remote_phy()
1686 	pause_adv = bnx2_phy_get_pause_adv(bp);  in bnx2_setup_remote_phy()
1688 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_remote_phy()
1690 		if (bp->advertising & ADVERTISED_10baseT_Half)  in bnx2_setup_remote_phy()
1692 		if (bp->advertising & ADVERTISED_10baseT_Full)  in bnx2_setup_remote_phy()
1694 		if (bp->advertising & ADVERTISED_100baseT_Half)  in bnx2_setup_remote_phy()
1696 		if (bp->advertising & ADVERTISED_100baseT_Full)  in bnx2_setup_remote_phy()
1698 		if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_remote_phy()
1700 		if (bp->advertising & ADVERTISED_2500baseX_Full)  in bnx2_setup_remote_phy()
1703 		if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_remote_phy()
1705 		else if (bp->req_line_speed == SPEED_1000)  in bnx2_setup_remote_phy()
1707 		else if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_remote_phy()
1708 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1712 		} else if (bp->req_line_speed == SPEED_10) {  in bnx2_setup_remote_phy()
1713 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1729 	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);  in bnx2_setup_remote_phy()
1731 	spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1732 	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);  in bnx2_setup_remote_phy()
1733 	spin_lock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1739 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_serdes_phy()  argument
1740 __releases(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1741 __acquires(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1746 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_setup_serdes_phy()
1747 		return bnx2_setup_remote_phy(bp, port);  in bnx2_setup_serdes_phy()
1749 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_setup_serdes_phy()
1753 		if (bp->req_line_speed == SPEED_2500) {  in bnx2_setup_serdes_phy()
1754 			if (!bnx2_test_and_enable_2g5(bp))  in bnx2_setup_serdes_phy()
1756 		} else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1757 			if (bnx2_test_and_disable_2g5(bp))  in bnx2_setup_serdes_phy()
1760 		bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1763 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1767 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_serdes_phy()
1768 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1769 				bnx2_enable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1770 			else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1771 				bnx2_disable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1775 		} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_setup_serdes_phy()
1776 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1782 		if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_serdes_phy()
1792 			if (bp->link_up) {  in bnx2_setup_serdes_phy()
1793 				bnx2_write_phy(bp, bp->mii_adv, adv &  in bnx2_setup_serdes_phy()
1796 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |  in bnx2_setup_serdes_phy()
1799 				bp->link_up = 0;  in bnx2_setup_serdes_phy()
1800 				netif_carrier_off(bp->dev);  in bnx2_setup_serdes_phy()
1801 				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1802 				bnx2_report_link(bp);  in bnx2_setup_serdes_phy()
1804 			bnx2_write_phy(bp, bp->mii_adv, adv);  in bnx2_setup_serdes_phy()
1805 			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1807 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1808 			bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1813 	bnx2_test_and_enable_2g5(bp);  in bnx2_setup_serdes_phy()
1815 	if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_serdes_phy()
1818 	new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_serdes_phy()
1820 	bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1821 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1823 	bp->serdes_an_pending = 0;  in bnx2_setup_serdes_phy()
1826 		if (bp->link_up) {  in bnx2_setup_serdes_phy()
1827 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_serdes_phy()
1828 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1830 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1833 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_serdes_phy()
1834 		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |  in bnx2_setup_serdes_phy()
1844 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_setup_serdes_phy()
1845 		bp->serdes_an_pending = 1;  in bnx2_setup_serdes_phy()
1846 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_setup_serdes_phy()
1848 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1849 		bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1856 	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1871 bnx2_set_default_remote_link(struct bnx2 *bp)  in bnx2_set_default_remote_link()  argument
1875 	if (bp->phy_port == PORT_TP)  in bnx2_set_default_remote_link()
1876 		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);  in bnx2_set_default_remote_link()
1878 		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);  in bnx2_set_default_remote_link()
1881 		bp->req_line_speed = 0;  in bnx2_set_default_remote_link()
1882 		bp->autoneg |= AUTONEG_SPEED;  in bnx2_set_default_remote_link()
1883 		bp->advertising = ADVERTISED_Autoneg;  in bnx2_set_default_remote_link()
1885 			bp->advertising |= ADVERTISED_10baseT_Half;  in bnx2_set_default_remote_link()
1887 			bp->advertising |= ADVERTISED_10baseT_Full;  in bnx2_set_default_remote_link()
1889 			bp->advertising |= ADVERTISED_100baseT_Half;  in bnx2_set_default_remote_link()
1891 			bp->advertising |= ADVERTISED_100baseT_Full;  in bnx2_set_default_remote_link()
1893 			bp->advertising |= ADVERTISED_1000baseT_Full;  in bnx2_set_default_remote_link()
1895 			bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_set_default_remote_link()
1897 		bp->autoneg = 0;  in bnx2_set_default_remote_link()
1898 		bp->advertising = 0;  in bnx2_set_default_remote_link()
1899 		bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_remote_link()
1901 			bp->req_line_speed = SPEED_10;  in bnx2_set_default_remote_link()
1903 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1906 			bp->req_line_speed = SPEED_100;  in bnx2_set_default_remote_link()
1908 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1911 			bp->req_line_speed = SPEED_1000;  in bnx2_set_default_remote_link()
1913 			bp->req_line_speed = SPEED_2500;  in bnx2_set_default_remote_link()
1918 bnx2_set_default_link(struct bnx2 *bp)  in bnx2_set_default_link()  argument
1920 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_set_default_link()
1921 		bnx2_set_default_remote_link(bp);  in bnx2_set_default_link()
1925 	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;  in bnx2_set_default_link()
1926 	bp->req_line_speed = 0;  in bnx2_set_default_link()
1927 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_default_link()
1930 		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1932 		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);  in bnx2_set_default_link()
1935 			bp->autoneg = 0;  in bnx2_set_default_link()
1936 			bp->req_line_speed = bp->line_speed = SPEED_1000;  in bnx2_set_default_link()
1937 			bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_link()
1940 		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1944 bnx2_send_heart_beat(struct bnx2 *bp)  in bnx2_send_heart_beat()  argument
1949 	spin_lock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1950 	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);  in bnx2_send_heart_beat()
1951 	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;  in bnx2_send_heart_beat()
1952 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1953 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
1954 	spin_unlock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1958 bnx2_remote_phy_event(struct bnx2 *bp)  in bnx2_remote_phy_event()  argument
1961 	u8 link_up = bp->link_up;  in bnx2_remote_phy_event()
1964 	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_remote_phy_event()
1967 		bnx2_send_heart_beat(bp);  in bnx2_remote_phy_event()
1972 		bp->link_up = 0;  in bnx2_remote_phy_event()
1976 		bp->link_up = 1;  in bnx2_remote_phy_event()
1978 		bp->duplex = DUPLEX_FULL;  in bnx2_remote_phy_event()
1981 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
1984 				bp->line_speed = SPEED_10;  in bnx2_remote_phy_event()
1987 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
1991 				bp->line_speed = SPEED_100;  in bnx2_remote_phy_event()
1994 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
1997 				bp->line_speed = SPEED_1000;  in bnx2_remote_phy_event()
2000 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2003 				bp->line_speed = SPEED_2500;  in bnx2_remote_phy_event()
2006 				bp->line_speed = 0;  in bnx2_remote_phy_event()
2010 		bp->flow_ctrl = 0;  in bnx2_remote_phy_event()
2011 		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_remote_phy_event()
2013 			if (bp->duplex == DUPLEX_FULL)  in bnx2_remote_phy_event()
2014 				bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_remote_phy_event()
2017 				bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_remote_phy_event()
2019 				bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_remote_phy_event()
2022 		old_port = bp->phy_port;  in bnx2_remote_phy_event()
2024 			bp->phy_port = PORT_FIBRE;  in bnx2_remote_phy_event()
2026 			bp->phy_port = PORT_TP;  in bnx2_remote_phy_event()
2028 		if (old_port != bp->phy_port)  in bnx2_remote_phy_event()
2029 			bnx2_set_default_link(bp);  in bnx2_remote_phy_event()
2032 	if (bp->link_up != link_up)  in bnx2_remote_phy_event()
2033 		bnx2_report_link(bp);  in bnx2_remote_phy_event()
2035 	bnx2_set_mac_link(bp);  in bnx2_remote_phy_event()
2039 bnx2_set_remote_link(struct bnx2 *bp)  in bnx2_set_remote_link()  argument
2043 	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);  in bnx2_set_remote_link()
2046 			bnx2_remote_phy_event(bp);  in bnx2_set_remote_link()
2050 			bnx2_send_heart_beat(bp);  in bnx2_set_remote_link()
2057 bnx2_setup_copper_phy(struct bnx2 *bp)  in bnx2_setup_copper_phy()  argument
2058 __releases(&bp->phy_lock)  in bnx2_setup_copper_phy()
2059 __acquires(&bp->phy_lock)  in bnx2_setup_copper_phy()
2064 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_copper_phy()
2066 	bnx2_read_phy(bp, bp->mii_adv, &adv_reg);  in bnx2_setup_copper_phy()
2070 	new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);  in bnx2_setup_copper_phy()
2072 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_copper_phy()
2076 		new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_copper_phy()
2078 		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);  in bnx2_setup_copper_phy()
2081 		new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);  in bnx2_setup_copper_phy()
2086 			bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2087 			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);  in bnx2_setup_copper_phy()
2088 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |  in bnx2_setup_copper_phy()
2091 		else if (bp->link_up) {  in bnx2_setup_copper_phy()
2095 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2096 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2103 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2106 	if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_copper_phy()
2109 	if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_copper_phy()
2115 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2116 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2120 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_copper_phy()
2121 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2123 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2125 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2126 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2129 		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_copper_phy()
2136 			bp->line_speed = bp->req_line_speed;  in bnx2_setup_copper_phy()
2137 			bp->duplex = bp->req_duplex;  in bnx2_setup_copper_phy()
2138 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2139 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2142 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2143 		bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2149 bnx2_setup_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_phy()  argument
2150 __releases(&bp->phy_lock)  in bnx2_setup_phy()
2151 __acquires(&bp->phy_lock)  in bnx2_setup_phy()
2153 	if (bp->loopback == MAC_LOOPBACK)  in bnx2_setup_phy()
2156 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_setup_phy()
2157 		return bnx2_setup_serdes_phy(bp, port);  in bnx2_setup_phy()
2160 		return bnx2_setup_copper_phy(bp);  in bnx2_setup_phy()
2165 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5709s_phy()  argument
2169 	bp->mii_bmcr = MII_BMCR + 0x10;  in bnx2_init_5709s_phy()
2170 	bp->mii_bmsr = MII_BMSR + 0x10;  in bnx2_init_5709s_phy()
2171 	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;  in bnx2_init_5709s_phy()
2172 	bp->mii_adv = MII_ADVERTISE + 0x10;  in bnx2_init_5709s_phy()
2173 	bp->mii_lpa = MII_LPA + 0x10;  in bnx2_init_5709s_phy()
2174 	bp->mii_up1 = MII_BNX2_OVER1G_UP1;  in bnx2_init_5709s_phy()
2176 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);  in bnx2_init_5709s_phy()
2177 	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);  in bnx2_init_5709s_phy()
2179 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2181 		bnx2_reset_phy(bp);  in bnx2_init_5709s_phy()
2183 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);  in bnx2_init_5709s_phy()
2185 	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);  in bnx2_init_5709s_phy()
2188 	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);  in bnx2_init_5709s_phy()
2190 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_init_5709s_phy()
2191 	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);  in bnx2_init_5709s_phy()
2192 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_init_5709s_phy()
2196 	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);  in bnx2_init_5709s_phy()
2198 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);  in bnx2_init_5709s_phy()
2199 	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);  in bnx2_init_5709s_phy()
2201 	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);  in bnx2_init_5709s_phy()
2203 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);  in bnx2_init_5709s_phy()
2207 	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);  in bnx2_init_5709s_phy()
2209 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2215 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5708s_phy()  argument
2220 		bnx2_reset_phy(bp);  in bnx2_init_5708s_phy()
2222 	bp->mii_up1 = BCM5708S_UP1;  in bnx2_init_5708s_phy()
2224 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);  in bnx2_init_5708s_phy()
2225 	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);  in bnx2_init_5708s_phy()
2226 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2228 	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);  in bnx2_init_5708s_phy()
2230 	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);  in bnx2_init_5708s_phy()
2232 	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);  in bnx2_init_5708s_phy()
2234 	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);  in bnx2_init_5708s_phy()
2236 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {  in bnx2_init_5708s_phy()
2237 		bnx2_read_phy(bp, BCM5708S_UP1, &val);  in bnx2_init_5708s_phy()
2239 		bnx2_write_phy(bp, BCM5708S_UP1, val);  in bnx2_init_5708s_phy()
2242 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_5708s_phy()
2243 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_5708s_phy()
2244 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {  in bnx2_init_5708s_phy()
2246 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2248 		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);  in bnx2_init_5708s_phy()
2250 		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);  in bnx2_init_5708s_phy()
2251 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2254 	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &  in bnx2_init_5708s_phy()
2260 		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_5708s_phy()
2262 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2264 			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);  in bnx2_init_5708s_phy()
2265 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2273 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5706s_phy()  argument
2276 		bnx2_reset_phy(bp);  in bnx2_init_5706s_phy()
2278 	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_init_5706s_phy()
2280 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_5706s_phy()
2281 		BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2283 	if (bp->dev->mtu > 1500) {  in bnx2_init_5706s_phy()
2287 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2288 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2289 		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);  in bnx2_init_5706s_phy()
2291 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2292 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2293 		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);  in bnx2_init_5706s_phy()
2298 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2299 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2300 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_5706s_phy()
2302 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2303 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2304 		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);  in bnx2_init_5706s_phy()
2311 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_copper_phy()  argument
2316 		bnx2_reset_phy(bp);  in bnx2_init_copper_phy()
2318 	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {  in bnx2_init_copper_phy()
2319 		bnx2_write_phy(bp, 0x18, 0x0c00);  in bnx2_init_copper_phy()
2320 		bnx2_write_phy(bp, 0x17, 0x000a);  in bnx2_init_copper_phy()
2321 		bnx2_write_phy(bp, 0x15, 0x310b);  in bnx2_init_copper_phy()
2322 		bnx2_write_phy(bp, 0x17, 0x201f);  in bnx2_init_copper_phy()
2323 		bnx2_write_phy(bp, 0x15, 0x9506);  in bnx2_init_copper_phy()
2324 		bnx2_write_phy(bp, 0x17, 0x401f);  in bnx2_init_copper_phy()
2325 		bnx2_write_phy(bp, 0x15, 0x14e2);  in bnx2_init_copper_phy()
2326 		bnx2_write_phy(bp, 0x18, 0x0400);  in bnx2_init_copper_phy()
2329 	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {  in bnx2_init_copper_phy()
2330 		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,  in bnx2_init_copper_phy()
2332 		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_init_copper_phy()
2334 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);  in bnx2_init_copper_phy()
2337 	if (bp->dev->mtu > 1500) {  in bnx2_init_copper_phy()
2339 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2340 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2341 		bnx2_write_phy(bp, 0x18, val | 0x4000);  in bnx2_init_copper_phy()
2343 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2344 		bnx2_write_phy(bp, 0x10, val | 0x1);  in bnx2_init_copper_phy()
2347 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2348 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2349 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_copper_phy()
2351 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2352 		bnx2_write_phy(bp, 0x10, val & ~0x1);  in bnx2_init_copper_phy()
2356 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);  in bnx2_init_copper_phy()
2357 	bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);  in bnx2_init_copper_phy()
2361 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_copper_phy()
2364 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);  in bnx2_init_copper_phy()
2370 bnx2_init_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_phy()  argument
2371 __releases(&bp->phy_lock)  in bnx2_init_phy()
2372 __acquires(&bp->phy_lock)  in bnx2_init_phy()
2377 	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;  in bnx2_init_phy()
2378 	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;  in bnx2_init_phy()
2380 	bp->mii_bmcr = MII_BMCR;  in bnx2_init_phy()
2381 	bp->mii_bmsr = MII_BMSR;  in bnx2_init_phy()
2382 	bp->mii_bmsr1 = MII_BMSR;  in bnx2_init_phy()
2383 	bp->mii_adv = MII_ADVERTISE;  in bnx2_init_phy()
2384 	bp->mii_lpa = MII_LPA;  in bnx2_init_phy()
2386 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2388 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_phy()
2391 	bnx2_read_phy(bp, MII_PHYSID1, &val);  in bnx2_init_phy()
2392 	bp->phy_id = val << 16;  in bnx2_init_phy()
2393 	bnx2_read_phy(bp, MII_PHYSID2, &val);  in bnx2_init_phy()
2394 	bp->phy_id |= val & 0xffff;  in bnx2_init_phy()
2396 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_phy()
2397 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_phy()
2398 			rc = bnx2_init_5706s_phy(bp, reset_phy);  in bnx2_init_phy()
2399 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_phy()
2400 			rc = bnx2_init_5708s_phy(bp, reset_phy);  in bnx2_init_phy()
2401 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_phy()
2402 			rc = bnx2_init_5709s_phy(bp, reset_phy);  in bnx2_init_phy()
2405 		rc = bnx2_init_copper_phy(bp, reset_phy);  in bnx2_init_phy()
2410 		rc = bnx2_setup_phy(bp, bp->phy_port);  in bnx2_init_phy()
2416 bnx2_set_mac_loopback(struct bnx2 *bp)  in bnx2_set_mac_loopback()  argument
2420 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_loopback()
2423 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2424 	bp->link_up = 1;  in bnx2_set_mac_loopback()
2431 bnx2_set_phy_loopback(struct bnx2 *bp)  in bnx2_set_phy_loopback()  argument
2436 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2437 	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |  in bnx2_set_phy_loopback()
2439 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2444 		if (bnx2_test_link(bp) == 0)  in bnx2_set_phy_loopback()
2449 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_phy_loopback()
2455 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2456 	bp->link_up = 1;  in bnx2_set_phy_loopback()
2461 bnx2_dump_mcp_state(struct bnx2 *bp)  in bnx2_dump_mcp_state()  argument
2463 	struct net_device *dev = bp->dev;  in bnx2_dump_mcp_state()
2467 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_dump_mcp_state()
2475 		   bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));  in bnx2_dump_mcp_state()
2477 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),  in bnx2_dump_mcp_state()
2478 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),  in bnx2_dump_mcp_state()
2479 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));  in bnx2_dump_mcp_state()
2481 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2482 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2483 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));  in bnx2_dump_mcp_state()
2486 		   bnx2_shmem_rd(bp, BNX2_DRV_MB),  in bnx2_dump_mcp_state()
2487 		   bnx2_shmem_rd(bp, BNX2_FW_MB),  in bnx2_dump_mcp_state()
2488 		   bnx2_shmem_rd(bp, BNX2_LINK_STATUS));  in bnx2_dump_mcp_state()
2489 	pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));  in bnx2_dump_mcp_state()
2491 		   bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),  in bnx2_dump_mcp_state()
2492 		   bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));  in bnx2_dump_mcp_state()
2494 		bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));  in bnx2_dump_mcp_state()
2495 	DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);  in bnx2_dump_mcp_state()
2496 	DP_SHMEM_LINE(bp, 0x3cc);  in bnx2_dump_mcp_state()
2497 	DP_SHMEM_LINE(bp, 0x3dc);  in bnx2_dump_mcp_state()
2498 	DP_SHMEM_LINE(bp, 0x3ec);  in bnx2_dump_mcp_state()
2499 	netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));  in bnx2_dump_mcp_state()
2504 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)  in bnx2_fw_sync()  argument
2509 	bp->fw_wr_seq++;  in bnx2_fw_sync()
2510 	msg_data |= bp->fw_wr_seq;  in bnx2_fw_sync()
2511 	bp->fw_last_msg = msg_data;  in bnx2_fw_sync()
2513 	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2522 		val = bnx2_shmem_rd(bp, BNX2_FW_MB);  in bnx2_fw_sync()
2535 		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2538 			bnx2_dump_mcp_state(bp);  in bnx2_fw_sync()
2551 bnx2_init_5709_context(struct bnx2 *bp)  in bnx2_init_5709_context()  argument
2558 	BNX2_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2560 		val = BNX2_RD(bp, BNX2_CTX_COMMAND);  in bnx2_init_5709_context()
2568 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_init_5709_context()
2571 		if (bp->ctx_blk[i])  in bnx2_init_5709_context()
2572 			memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);  in bnx2_init_5709_context()
2576 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2577 			(bp->ctx_blk_mapping[i] & 0xffffffff) |  in bnx2_init_5709_context()
2579 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2580 			(u64) bp->ctx_blk_mapping[i] >> 32);  in bnx2_init_5709_context()
2581 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2585 			val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);  in bnx2_init_5709_context()
2599 bnx2_init_context(struct bnx2 *bp)  in bnx2_init_context()  argument
2610 		if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_context()
2631 			BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2632 			BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2636 				bnx2_ctx_wr(bp, vcid_addr, offset, 0);  in bnx2_init_context()
2642 bnx2_alloc_bad_rbuf(struct bnx2 *bp)  in bnx2_alloc_bad_rbuf()  argument
2652 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2658 	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2660 		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,  in bnx2_alloc_bad_rbuf()
2663 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);  in bnx2_alloc_bad_rbuf()
2673 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2684 		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);  in bnx2_alloc_bad_rbuf()
2691 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)  in bnx2_set_mac_addr()  argument
2697 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2702 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2706 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_page()  argument
2716 	mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,  in bnx2_alloc_rx_page()
2718 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_page()
2731 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)  in bnx2_free_rx_page()  argument
2739 	dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),  in bnx2_free_rx_page()
2747 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_data()  argument
2755 	data = kmalloc(bp->rx_buf_size, gfp);  in bnx2_alloc_rx_data()
2759 	mapping = dma_map_single(&bp->pdev->dev,  in bnx2_alloc_rx_data()
2761 				 bp->rx_buf_use_size,  in bnx2_alloc_rx_data()
2763 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_data()
2774 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_alloc_rx_data()
2780 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)  in bnx2_phy_event_is_set()  argument
2790 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2792 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
2800 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_phy_int()  argument
2802 	spin_lock(&bp->phy_lock);  in bnx2_phy_int()
2804 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))  in bnx2_phy_int()
2805 		bnx2_set_link(bp);  in bnx2_phy_int()
2806 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))  in bnx2_phy_int()
2807 		bnx2_set_remote_link(bp);  in bnx2_phy_int()
2809 	spin_unlock(&bp->phy_lock);  in bnx2_phy_int()
2828 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_tx_int()  argument
2836 	index = (bnapi - bp->bnx2_napi);  in bnx2_tx_int()
2837 	txq = netdev_get_tx_queue(bp->dev, index);  in bnx2_tx_int()
2869 		dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_tx_int()
2881 			dma_unmap_page(&bp->pdev->dev,  in bnx2_tx_int()
2911 		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {  in bnx2_tx_int()
2914 		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))  in bnx2_tx_int()
2923 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_skb_pages()  argument
2981 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_data()  argument
2990 	dma_sync_single_for_device(&bp->pdev->dev,  in bnx2_reuse_rx_data()
2994 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_reuse_rx_data()
3011 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,  in bnx2_rx_skb()  argument
3019 	err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);  in bnx2_rx_skb()
3021 		bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);  in bnx2_rx_skb()
3027 			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_skb()
3032 	dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,  in bnx2_rx_skb()
3062 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,  in bnx2_rx_skb()
3087 			err = bnx2_alloc_rx_page(bp, rxr,  in bnx2_rx_skb()
3093 				bnx2_reuse_rx_skb_pages(bp, rxr, skb,  in bnx2_rx_skb()
3098 			dma_unmap_page(&bp->pdev->dev, mapping_old,  in bnx2_rx_skb()
3130 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_rx_int()  argument
3169 		dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,  in bnx2_rx_int()
3184 		} else if (len > bp->rx_jumbo_thresh) {  in bnx2_rx_int()
3185 			hdr_len = bp->rx_jumbo_thresh;  in bnx2_rx_int()
3195 			bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3202 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_int()
3209 		if (len <= bp->rx_copy_thresh) {  in bnx2_rx_int()
3210 			skb = netdev_alloc_skb(bp->dev, len + 6);  in bnx2_rx_int()
3212 				bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3224 			bnx2_reuse_rx_data(bp, rxr, data,  in bnx2_rx_int()
3228 			skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,  in bnx2_rx_int()
3234 		    !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))  in bnx2_rx_int()
3237 		skb->protocol = eth_type_trans(skb, bp->dev);  in bnx2_rx_int()
3239 		if (len > (bp->dev->mtu + ETH_HLEN) &&  in bnx2_rx_int()
3249 		if ((bp->dev->features & NETIF_F_RXCSUM) &&  in bnx2_rx_int()
3257 		if ((bp->dev->features & NETIF_F_RXHASH) &&  in bnx2_rx_int()
3263 		skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);  in bnx2_rx_int()
3284 		BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_rx_int()
3286 	BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);  in bnx2_rx_int()
3288 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3303 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi()  local
3306 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3311 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi()
3323 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi_1shot()  local
3328 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi_1shot()
3340 	struct bnx2 *bp = bnapi->bp;  in bnx2_interrupt()  local
3350 	    (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &  in bnx2_interrupt()
3354 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3361 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_interrupt()
3364 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_interrupt()
3411 bnx2_chk_missed_msi(struct bnx2 *bp)  in bnx2_chk_missed_msi()  argument
3413 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_chk_missed_msi()
3417 		msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);  in bnx2_chk_missed_msi()
3421 		if (bnapi->last_status_idx == bp->idle_chk_status_idx) {  in bnx2_chk_missed_msi()
3422 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3424 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3425 			bnx2_msi(bp->irq_tbl[0].vector, bnapi);  in bnx2_chk_missed_msi()
3429 	bp->idle_chk_status_idx = bnapi->last_status_idx;  in bnx2_chk_missed_msi()
3433 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_cnic()  argument
3441 	c_ops = rcu_dereference(bp->cnic_ops);  in bnx2_poll_cnic()
3443 		bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,  in bnx2_poll_cnic()
3449 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_link()  argument
3458 		bnx2_phy_int(bp, bnapi);  in bnx2_poll_link()
3463 		BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3464 			bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_poll_link()
3465 		BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_poll_link()
3469 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,  in bnx2_poll_work()  argument
3476 		bnx2_tx_int(bp, bnapi, 0);  in bnx2_poll_work()
3479 		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);  in bnx2_poll_work()
3487 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll_msix()  local
3492 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll_msix()
3502 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3514 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll()  local
3519 		bnx2_poll_link(bp, bnapi);  in bnx2_poll()
3521 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll()
3524 		bnx2_poll_cnic(bp, bnapi);  in bnx2_poll()
3539 			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {  in bnx2_poll()
3540 				BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3545 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3550 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3566 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_rx_mode()  local
3574 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3576 	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |  in bnx2_set_rx_mode()
3580 	     (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_set_rx_mode()
3590 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3613 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3628 			bnx2_set_mac_addr(bp, ha->addr,  in bnx2_set_rx_mode()
3637 	if (rx_mode != bp->rx_mode) {  in bnx2_set_rx_mode()
3638 		bp->rx_mode = rx_mode;  in bnx2_set_rx_mode()
3639 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3642 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3643 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3644 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3646 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3676 static void bnx2_release_firmware(struct bnx2 *bp)  in bnx2_release_firmware()  argument
3678 	if (bp->rv2p_firmware) {  in bnx2_release_firmware()
3679 		release_firmware(bp->mips_firmware);  in bnx2_release_firmware()
3680 		release_firmware(bp->rv2p_firmware);  in bnx2_release_firmware()
3681 		bp->rv2p_firmware = NULL;  in bnx2_release_firmware()
3685 static int bnx2_request_uncached_firmware(struct bnx2 *bp)  in bnx2_request_uncached_firmware()  argument
3692 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_request_uncached_firmware()
3694 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||  in bnx2_request_uncached_firmware()
3695 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))  in bnx2_request_uncached_firmware()
3704 	rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3710 	rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3715 	mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_request_uncached_firmware()
3716 	rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_request_uncached_firmware()
3717 	if (bp->mips_firmware->size < sizeof(*mips_fw) ||  in bnx2_request_uncached_firmware()
3718 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||  in bnx2_request_uncached_firmware()
3719 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||  in bnx2_request_uncached_firmware()
3720 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||  in bnx2_request_uncached_firmware()
3721 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||  in bnx2_request_uncached_firmware()
3722 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {  in bnx2_request_uncached_firmware()
3727 	if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||  in bnx2_request_uncached_firmware()
3728 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||  in bnx2_request_uncached_firmware()
3729 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {  in bnx2_request_uncached_firmware()
3738 	release_firmware(bp->rv2p_firmware);  in bnx2_request_uncached_firmware()
3739 	bp->rv2p_firmware = NULL;  in bnx2_request_uncached_firmware()
3741 	release_firmware(bp->mips_firmware);  in bnx2_request_uncached_firmware()
3745 static int bnx2_request_firmware(struct bnx2 *bp)  in bnx2_request_firmware()  argument
3747 	return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);  in bnx2_request_firmware()
3763 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,  in load_rv2p_fw()  argument
3774 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3785 		BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3787 		BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3791 		BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3794 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3801 			BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3804 			BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3807 			BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3813 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3816 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3823 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,  in load_cpu_fw()  argument
3832 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3834 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3835 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3841 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3848 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3855 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3862 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3869 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3876 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3880 	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);  in load_cpu_fw()
3883 	bnx2_reg_wr_ind(bp, cpu_reg->pc, val);  in load_cpu_fw()
3886 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3888 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3889 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3895 bnx2_init_cpus(struct bnx2 *bp)  in bnx2_init_cpus()  argument
3898 		(const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_init_cpus()
3900 		(const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_init_cpus()
3904 	load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);  in bnx2_init_cpus()
3905 	load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);  in bnx2_init_cpus()
3908 	rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);  in bnx2_init_cpus()
3913 	rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);  in bnx2_init_cpus()
3918 	rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);  in bnx2_init_cpus()
3923 	rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);  in bnx2_init_cpus()
3928 	rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);  in bnx2_init_cpus()
3935 bnx2_setup_wol(struct bnx2 *bp)  in bnx2_setup_wol()  argument
3940 	if (bp->wol) {  in bnx2_setup_wol()
3944 		autoneg = bp->autoneg;  in bnx2_setup_wol()
3945 		advertising = bp->advertising;  in bnx2_setup_wol()
3947 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3948 			bp->autoneg = AUTONEG_SPEED;  in bnx2_setup_wol()
3949 			bp->advertising = ADVERTISED_10baseT_Half |  in bnx2_setup_wol()
3956 		spin_lock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3957 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_setup_wol()
3958 		spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3960 		bp->autoneg = autoneg;  in bnx2_setup_wol()
3961 		bp->advertising = advertising;  in bnx2_setup_wol()
3963 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_setup_wol()
3965 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_setup_wol()
3972 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3976 			if (bp->line_speed == SPEED_2500)  in bnx2_setup_wol()
3980 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_setup_wol()
3984 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_setup_wol()
3987 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);  in bnx2_setup_wol()
3990 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_setup_wol()
3991 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_setup_wol()
3992 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);  in bnx2_setup_wol()
3995 		BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_setup_wol()
4000 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_setup_wol()
4002 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_setup_wol()
4009 	if (!(bp->flags & BNX2_FLAG_NO_WOL)) {  in bnx2_setup_wol()
4013 		if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {  in bnx2_setup_wol()
4014 			bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4020 		val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_setup_wol()
4021 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,  in bnx2_setup_wol()
4023 		bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4024 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);  in bnx2_setup_wol()
4030 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)  in bnx2_set_power_state()  argument
4036 		pci_enable_wake(bp->pdev, PCI_D0, false);  in bnx2_set_power_state()
4037 		pci_set_power_state(bp->pdev, PCI_D0);  in bnx2_set_power_state()
4039 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_power_state()
4042 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
4044 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_set_power_state()
4046 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4050 		bnx2_setup_wol(bp);  in bnx2_set_power_state()
4051 		pci_wake_from_d3(bp->pdev, bp->wol);  in bnx2_set_power_state()
4052 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_set_power_state()
4053 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {  in bnx2_set_power_state()
4055 			if (bp->wol)  in bnx2_set_power_state()
4056 				pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4060 		if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_set_power_state()
4067 			val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_set_power_state()
4070 			bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);  in bnx2_set_power_state()
4072 		pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4086 bnx2_acquire_nvram_lock(struct bnx2 *bp)  in bnx2_acquire_nvram_lock()  argument
4092 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4094 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_acquire_nvram_lock()
4108 bnx2_release_nvram_lock(struct bnx2 *bp)  in bnx2_release_nvram_lock()  argument
4114 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4117 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_release_nvram_lock()
4132 bnx2_enable_nvram_write(struct bnx2 *bp)  in bnx2_enable_nvram_write()  argument
4136 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_enable_nvram_write()
4137 	BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4139 	if (bp->flash_info->flags & BNX2_NV_WREN) {  in bnx2_enable_nvram_write()
4142 		BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4143 		BNX2_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4149 			val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_enable_nvram_write()
4161 bnx2_disable_nvram_write(struct bnx2 *bp)  in bnx2_disable_nvram_write()  argument
4165 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_disable_nvram_write()
4166 	BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4171 bnx2_enable_nvram_access(struct bnx2 *bp)  in bnx2_enable_nvram_access()  argument
4175 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_enable_nvram_access()
4177 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4182 bnx2_disable_nvram_access(struct bnx2 *bp)  in bnx2_disable_nvram_access()  argument
4186 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_disable_nvram_access()
4188 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4194 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)  in bnx2_nvram_erase_page()  argument
4199 	if (bp->flash_info->flags & BNX2_NV_BUFFERED)  in bnx2_nvram_erase_page()
4208 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4211 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4214 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4222 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_erase_page()
4234 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)  in bnx2_nvram_read_dword()  argument
4243 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_read_dword()
4244 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_read_dword()
4245 			   bp->flash_info->page_bits) +  in bnx2_nvram_read_dword()
4246 			  (offset % bp->flash_info->page_size);  in bnx2_nvram_read_dword()
4250 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4253 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4256 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4264 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_read_dword()
4266 			__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));  in bnx2_nvram_read_dword()
4279 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)  in bnx2_nvram_write_dword()  argument
4289 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_write_dword()
4290 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_write_dword()
4291 			  bp->flash_info->page_bits) +  in bnx2_nvram_write_dword()
4292 			 (offset % bp->flash_info->page_size);  in bnx2_nvram_write_dword()
4296 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4301 	BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4304 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4307 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4313 		if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)  in bnx2_nvram_write_dword()
4323 bnx2_init_nvram(struct bnx2 *bp)  in bnx2_init_nvram()  argument
4329 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_nvram()
4330 		bp->flash_info = &flash_5709;  in bnx2_init_nvram()
4335 	val = BNX2_RD(bp, BNX2_NVM_CFG1);  in bnx2_init_nvram()
4346 				bp->flash_info = flash;  in bnx2_init_nvram()
4364 				bp->flash_info = flash;  in bnx2_init_nvram()
4367 				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_init_nvram()
4371 				bnx2_enable_nvram_access(bp);  in bnx2_init_nvram()
4374 				BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4375 				BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4376 				BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4377 				BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4380 				bnx2_disable_nvram_access(bp);  in bnx2_init_nvram()
4381 				bnx2_release_nvram_lock(bp);  in bnx2_init_nvram()
4389 		bp->flash_info = NULL;  in bnx2_init_nvram()
4395 	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);  in bnx2_init_nvram()
4398 		bp->flash_size = val;  in bnx2_init_nvram()
4400 		bp->flash_size = bp->flash_info->total_size;  in bnx2_init_nvram()
4406 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,  in bnx2_nvram_read()  argument
4416 	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_read()
4420 	bnx2_enable_nvram_access(bp);  in bnx2_nvram_read()
4444 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4469 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4482 		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);  in bnx2_nvram_read()
4490 			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);  in bnx2_nvram_read()
4502 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4508 	bnx2_disable_nvram_access(bp);  in bnx2_nvram_read()
4510 	bnx2_release_nvram_lock(bp);  in bnx2_nvram_read()
4516 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,  in bnx2_nvram_write()  argument
4534 		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))  in bnx2_nvram_write()
4541 		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))  in bnx2_nvram_write()
4559 	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4575 		page_start -= (page_start % bp->flash_info->page_size);  in bnx2_nvram_write()
4577 		page_end = page_start + bp->flash_info->page_size;  in bnx2_nvram_write()
4585 		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_write()
4589 		bnx2_enable_nvram_access(bp);  in bnx2_nvram_write()
4592 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4597 			for (j = 0; j < bp->flash_info->page_size; j += 4) {  in bnx2_nvram_write()
4598 				if (j == (bp->flash_info->page_size - 4)) {  in bnx2_nvram_write()
4601 				rc = bnx2_nvram_read_dword(bp,  in bnx2_nvram_write()
4614 		if ((rc = bnx2_enable_nvram_write(bp)) != 0)  in bnx2_nvram_write()
4620 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4622 			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)  in bnx2_nvram_write()
4626 			bnx2_enable_nvram_write(bp);  in bnx2_nvram_write()
4631 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4644 				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&  in bnx2_nvram_write()
4649 			rc = bnx2_nvram_write_dword(bp, addr, buf,  in bnx2_nvram_write()
4661 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4668 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4679 		bnx2_disable_nvram_write(bp);  in bnx2_nvram_write()
4682 		bnx2_disable_nvram_access(bp);  in bnx2_nvram_write()
4683 		bnx2_release_nvram_lock(bp);  in bnx2_nvram_write()
4696 bnx2_init_fw_cap(struct bnx2 *bp)  in bnx2_init_fw_cap()  argument
4700 	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4701 	bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4703 	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))  in bnx2_init_fw_cap()
4704 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4706 	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);  in bnx2_init_fw_cap()
4711 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4715 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_init_fw_cap()
4719 		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4721 		link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_init_fw_cap()
4723 			bp->phy_port = PORT_FIBRE;  in bnx2_init_fw_cap()
4725 			bp->phy_port = PORT_TP;  in bnx2_init_fw_cap()
4731 	if (netif_running(bp->dev) && sig)  in bnx2_init_fw_cap()
4732 		bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);  in bnx2_init_fw_cap()
4736 bnx2_setup_msix_tbl(struct bnx2 *bp)  in bnx2_setup_msix_tbl()  argument
4738 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4740 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4741 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4745 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_chip()  argument
4753 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_reset_chip()
4754 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_reset_chip()
4755 		BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_reset_chip()
4760 		val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);  in bnx2_reset_chip()
4763 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4765 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_reset_chip()
4766 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4770 			val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);  in bnx2_reset_chip()
4777 	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);  in bnx2_reset_chip()
4781 	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,  in bnx2_reset_chip()
4786 	val = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_reset_chip()
4788 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_reset_chip()
4789 		BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4790 		BNX2_RD(bp, BNX2_MISC_COMMAND);  in bnx2_reset_chip()
4796 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4804 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4810 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_reset_chip()
4811 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))  in bnx2_reset_chip()
4816 			val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);  in bnx2_reset_chip()
4831 	val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);  in bnx2_reset_chip()
4838 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);  in bnx2_reset_chip()
4842 	spin_lock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4843 	old_port = bp->phy_port;  in bnx2_reset_chip()
4844 	bnx2_init_fw_cap(bp);  in bnx2_reset_chip()
4845 	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&  in bnx2_reset_chip()
4846 	    old_port != bp->phy_port)  in bnx2_reset_chip()
4847 		bnx2_set_default_remote_link(bp);  in bnx2_reset_chip()
4848 	spin_unlock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4850 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_reset_chip()
4853 		BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4856 		rc = bnx2_alloc_bad_rbuf(bp);  in bnx2_reset_chip()
4859 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_reset_chip()
4860 		bnx2_setup_msix_tbl(bp);  in bnx2_reset_chip()
4862 		BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4870 bnx2_init_chip(struct bnx2 *bp)  in bnx2_init_chip()  argument
4876 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4889 	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))  in bnx2_init_chip()
4892 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&  in bnx2_init_chip()
4893 	    (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&  in bnx2_init_chip()
4894 	    !(bp->flags & BNX2_FLAG_PCIX))  in bnx2_init_chip()
4897 	BNX2_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4899 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_chip()
4900 		val = BNX2_RD(bp, BNX2_TDMA_CONFIG);  in bnx2_init_chip()
4902 		BNX2_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4905 	if (bp->flags & BNX2_FLAG_PCIX) {  in bnx2_init_chip()
4908 		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4910 		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4914 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4921 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4922 		rc = bnx2_init_5709_context(bp);  in bnx2_init_chip()
4926 		bnx2_init_context(bp);  in bnx2_init_chip()
4928 	if ((rc = bnx2_init_cpus(bp)) != 0)  in bnx2_init_chip()
4931 	bnx2_init_nvram(bp);  in bnx2_init_chip()
4933 	bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_init_chip()
4935 	val = BNX2_RD(bp, BNX2_MQ_CONFIG);  in bnx2_init_chip()
4938 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4940 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_chip()
4944 	BNX2_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4947 	BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4948 	BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4951 	BNX2_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4954 	val = BNX2_RD(bp, BNX2_TBDR_CONFIG);  in bnx2_init_chip()
4957 	BNX2_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4959 	val = bp->mac_addr[0] +  in bnx2_init_chip()
4960 	      (bp->mac_addr[1] << 8) +  in bnx2_init_chip()
4961 	      (bp->mac_addr[2] << 16) +  in bnx2_init_chip()
4962 	      bp->mac_addr[3] +  in bnx2_init_chip()
4963 	      (bp->mac_addr[4] << 8) +  in bnx2_init_chip()
4964 	      (bp->mac_addr[5] << 16);  in bnx2_init_chip()
4965 	BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
4968 	mtu = bp->dev->mtu;  in bnx2_init_chip()
4972 	BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
4977 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));  in bnx2_init_chip()
4978 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));  in bnx2_init_chip()
4979 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));  in bnx2_init_chip()
4981 	memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);  in bnx2_init_chip()
4983 		bp->bnx2_napi[i].last_status_idx = 0;  in bnx2_init_chip()
4985 	bp->idle_chk_status_idx = 0xffff;  in bnx2_init_chip()
4988 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
4990 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
4991 		(u64) bp->status_blk_mapping & 0xffffffff);  in bnx2_init_chip()
4992 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
4994 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
4995 		(u64) bp->stats_blk_mapping & 0xffffffff);  in bnx2_init_chip()
4996 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
4997 		(u64) bp->stats_blk_mapping >> 32);  in bnx2_init_chip()
4999 	BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5000 		(bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);  in bnx2_init_chip()
5002 	BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5003 		(bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);  in bnx2_init_chip()
5005 	BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
5006 		(bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);  in bnx2_init_chip()
5008 	BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5010 	BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5012 	BNX2_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
5013 		(bp->com_ticks_int << 16) | bp->com_ticks);  in bnx2_init_chip()
5015 	BNX2_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
5016 		(bp->cmd_ticks_int << 16) | bp->cmd_ticks);  in bnx2_init_chip()
5018 	if (bp->flags & BNX2_FLAG_BROKEN_STATS)  in bnx2_init_chip()
5019 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
5021 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
5022 	BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
5024 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)  in bnx2_init_chip()
5031 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_init_chip()
5032 		BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
5038 	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)  in bnx2_init_chip()
5041 	BNX2_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5043 	if (bp->rx_ticks < 25)  in bnx2_init_chip()
5044 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);  in bnx2_init_chip()
5046 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);  in bnx2_init_chip()
5048 	for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_init_chip()
5052 		BNX2_WR(bp, base,  in bnx2_init_chip()
5057 		BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5058 			(bp->tx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5059 			 bp->tx_quick_cons_trip);  in bnx2_init_chip()
5061 		BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5062 			(bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5064 		BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5065 			(bp->rx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5066 			bp->rx_quick_cons_trip);  in bnx2_init_chip()
5068 		BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5069 			(bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5073 	BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5075 	BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5078 	bnx2_set_rx_mode(bp->dev);  in bnx2_init_chip()
5080 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
5081 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_init_chip()
5083 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5085 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,  in bnx2_init_chip()
5088 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5089 	BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);  in bnx2_init_chip()
5093 	bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_init_chip()
5099 bnx2_clear_ring_states(struct bnx2 *bp)  in bnx2_clear_ring_states()  argument
5107 		bnapi = &bp->bnx2_napi[i];  in bnx2_clear_ring_states()
5122 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)  in bnx2_init_tx_context()  argument
5127 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_tx_context()
5139 	bnx2_ctx_wr(bp, cid_addr, offset0, val);  in bnx2_init_tx_context()
5142 	bnx2_ctx_wr(bp, cid_addr, offset1, val);  in bnx2_init_tx_context()
5145 	bnx2_ctx_wr(bp, cid_addr, offset2, val);  in bnx2_init_tx_context()
5148 	bnx2_ctx_wr(bp, cid_addr, offset3, val);  in bnx2_init_tx_context()
5152 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_tx_ring()  argument
5159 	bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_tx_ring()
5167 	bp->tx_wake_thresh = bp->tx_ring_size / 2;  in bnx2_init_tx_ring()
5180 	bnx2_init_tx_context(bp, cid, txr);  in bnx2_init_tx_ring()
5208 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_rx_ring()  argument
5213 	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_rx_ring()
5224 			     bp->rx_buf_use_size, bp->rx_max_ring);  in bnx2_init_rx_ring()
5226 	bnx2_init_rx_context(bp, cid);  in bnx2_init_rx_ring()
5228 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_rx_ring()
5229 		val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);  in bnx2_init_rx_ring()
5230 		BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5233 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);  in bnx2_init_rx_ring()
5234 	if (bp->rx_pg_ring_size) {  in bnx2_init_rx_ring()
5237 				     PAGE_SIZE, bp->rx_max_pg_ring);  in bnx2_init_rx_ring()
5238 		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;  in bnx2_init_rx_ring()
5239 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);  in bnx2_init_rx_ring()
5240 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,  in bnx2_init_rx_ring()
5244 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5247 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5249 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_rx_ring()
5250 			BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5254 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5257 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5260 	for (i = 0; i < bp->rx_pg_ring_size; i++) {  in bnx2_init_rx_ring()
5261 		if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5262 			netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",  in bnx2_init_rx_ring()
5263 				    ring_num, i, bp->rx_pg_ring_size);  in bnx2_init_rx_ring()
5272 	for (i = 0; i < bp->rx_ring_size; i++) {  in bnx2_init_rx_ring()
5273 		if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5274 			netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",  in bnx2_init_rx_ring()
5275 				    ring_num, i, bp->rx_ring_size);  in bnx2_init_rx_ring()
5287 	BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_init_rx_ring()
5288 	BNX2_WR16(bp, rxr->rx_bidx_addr, prod);  in bnx2_init_rx_ring()
5290 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5294 bnx2_init_all_rings(struct bnx2 *bp)  in bnx2_init_all_rings()  argument
5299 	bnx2_clear_ring_states(bp);  in bnx2_init_all_rings()
5301 	BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5302 	for (i = 0; i < bp->num_tx_rings; i++)  in bnx2_init_all_rings()
5303 		bnx2_init_tx_ring(bp, i);  in bnx2_init_all_rings()
5305 	if (bp->num_tx_rings > 1)  in bnx2_init_all_rings()
5306 		BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5309 	BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5310 	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);  in bnx2_init_all_rings()
5312 	for (i = 0; i < bp->num_rx_rings; i++)  in bnx2_init_all_rings()
5313 		bnx2_init_rx_ring(bp, i);  in bnx2_init_all_rings()
5315 	if (bp->num_rx_rings > 1) {  in bnx2_init_all_rings()
5321 			tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;  in bnx2_init_all_rings()
5323 				BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5324 				BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5335 		BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5360 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)  in bnx2_set_rx_ring_size()  argument
5365 	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;  in bnx2_set_rx_ring_size()
5370 	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;  in bnx2_set_rx_ring_size()
5371 	bp->rx_pg_ring_size = 0;  in bnx2_set_rx_ring_size()
5372 	bp->rx_max_pg_ring = 0;  in bnx2_set_rx_ring_size()
5373 	bp->rx_max_pg_ring_idx = 0;  in bnx2_set_rx_ring_size()
5374 	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {  in bnx2_set_rx_ring_size()
5375 		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;  in bnx2_set_rx_ring_size()
5381 		bp->rx_pg_ring_size = jumbo_size;  in bnx2_set_rx_ring_size()
5382 		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,  in bnx2_set_rx_ring_size()
5384 		bp->rx_max_pg_ring_idx =  in bnx2_set_rx_ring_size()
5385 			(bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5387 		bp->rx_copy_thresh = 0;  in bnx2_set_rx_ring_size()
5390 	bp->rx_buf_use_size = rx_size;  in bnx2_set_rx_ring_size()
5392 	bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +  in bnx2_set_rx_ring_size()
5394 	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;  in bnx2_set_rx_ring_size()
5395 	bp->rx_ring_size = size;  in bnx2_set_rx_ring_size()
5396 	bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);  in bnx2_set_rx_ring_size()
5397 	bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5401 bnx2_free_tx_skbs(struct bnx2 *bp)  in bnx2_free_tx_skbs()  argument
5405 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_skbs()
5406 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_skbs()
5423 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5434 				dma_unmap_page(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5441 		netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));  in bnx2_free_tx_skbs()
5446 bnx2_free_rx_skbs(struct bnx2 *bp)  in bnx2_free_rx_skbs()  argument
5450 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_skbs()
5451 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_skbs()
5458 		for (j = 0; j < bp->rx_max_ring_idx; j++) {  in bnx2_free_rx_skbs()
5465 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_rx_skbs()
5467 					 bp->rx_buf_use_size,  in bnx2_free_rx_skbs()
5474 		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)  in bnx2_free_rx_skbs()
5475 			bnx2_free_rx_page(bp, rxr, j);  in bnx2_free_rx_skbs()
5480 bnx2_free_skbs(struct bnx2 *bp)  in bnx2_free_skbs()  argument
5482 	bnx2_free_tx_skbs(bp);  in bnx2_free_skbs()
5483 	bnx2_free_rx_skbs(bp);  in bnx2_free_skbs()
5487 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_nic()  argument
5491 	rc = bnx2_reset_chip(bp, reset_code);  in bnx2_reset_nic()
5492 	bnx2_free_skbs(bp);  in bnx2_reset_nic()
5496 	if ((rc = bnx2_init_chip(bp)) != 0)  in bnx2_reset_nic()
5499 	bnx2_init_all_rings(bp);  in bnx2_reset_nic()
5504 bnx2_init_nic(struct bnx2 *bp, int reset_phy)  in bnx2_init_nic()  argument
5508 	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)  in bnx2_init_nic()
5511 	spin_lock_bh(&bp->phy_lock);  in bnx2_init_nic()
5512 	bnx2_init_phy(bp, reset_phy);  in bnx2_init_nic()
5513 	bnx2_set_link(bp);  in bnx2_init_nic()
5514 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_nic()
5515 		bnx2_remote_phy_event(bp);  in bnx2_init_nic()
5516 	spin_unlock_bh(&bp->phy_lock);  in bnx2_init_nic()
5521 bnx2_shutdown_chip(struct bnx2 *bp)  in bnx2_shutdown_chip()  argument
5525 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_shutdown_chip()
5527 	else if (bp->wol)  in bnx2_shutdown_chip()
5532 	return bnx2_reset_chip(bp, reset_code);  in bnx2_shutdown_chip()
5536 bnx2_test_registers(struct bnx2 *bp)  in bnx2_test_registers()  argument
5657 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_registers()
5671 		save_val = readl(bp->regview + offset);  in bnx2_test_registers()
5673 		writel(0, bp->regview + offset);  in bnx2_test_registers()
5675 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5684 		writel(0xffffffff, bp->regview + offset);  in bnx2_test_registers()
5686 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5695 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5699 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5707 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)  in bnx2_do_mem_test()  argument
5718 			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);  in bnx2_do_mem_test()
5720 			if (bnx2_reg_rd_ind(bp, start + offset) !=  in bnx2_do_mem_test()
5730 bnx2_test_memory(struct bnx2 *bp)  in bnx2_test_memory()  argument
5756 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_memory()
5762 		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,  in bnx2_test_memory()
5775 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)  in bnx2_run_loopback()  argument
5787 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;  in bnx2_run_loopback()
5796 		bp->loopback = MAC_LOOPBACK;  in bnx2_run_loopback()
5797 		bnx2_set_mac_loopback(bp);  in bnx2_run_loopback()
5800 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_run_loopback()
5803 		bp->loopback = PHY_LOOPBACK;  in bnx2_run_loopback()
5804 		bnx2_set_phy_loopback(bp);  in bnx2_run_loopback()
5809 	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);  in bnx2_run_loopback()
5810 	skb = netdev_alloc_skb(bp->dev, pkt_size);  in bnx2_run_loopback()
5814 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);  in bnx2_run_loopback()
5819 	map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,  in bnx2_run_loopback()
5821 	if (dma_mapping_error(&bp->pdev->dev, map)) {  in bnx2_run_loopback()
5826 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5827 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5829 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5847 	BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);  in bnx2_run_loopback()
5848 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5852 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5853 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5855 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5859 	dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);  in bnx2_run_loopback()
5876 	dma_sync_single_for_cpu(&bp->pdev->dev,  in bnx2_run_loopback()
5878 		bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);  in bnx2_run_loopback()
5903 	bp->loopback = 0;  in bnx2_run_loopback()
5913 bnx2_test_loopback(struct bnx2 *bp)  in bnx2_test_loopback()  argument
5917 	if (!netif_running(bp->dev))  in bnx2_test_loopback()
5920 	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_test_loopback()
5921 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5922 	bnx2_init_phy(bp, 1);  in bnx2_test_loopback()
5923 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5924 	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))  in bnx2_test_loopback()
5926 	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))  in bnx2_test_loopback()
5935 bnx2_test_nvram(struct bnx2 *bp)  in bnx2_test_nvram()  argument
5942 	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)  in bnx2_test_nvram()
5951 	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)  in bnx2_test_nvram()
5970 bnx2_test_link(struct bnx2 *bp)  in bnx2_test_link()  argument
5974 	if (!netif_running(bp->dev))  in bnx2_test_link()
5977 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_test_link()
5978 		if (bp->link_up)  in bnx2_test_link()
5982 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_link()
5983 	bnx2_enable_bmsr1(bp);  in bnx2_test_link()
5984 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
5985 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
5986 	bnx2_disable_bmsr1(bp);  in bnx2_test_link()
5987 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_link()
5996 bnx2_test_intr(struct bnx2 *bp)  in bnx2_test_intr()  argument
6001 	if (!netif_running(bp->dev))  in bnx2_test_intr()
6004 	status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;  in bnx2_test_intr()
6007 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6008 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_test_intr()
6011 		if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=  in bnx2_test_intr()
6027 bnx2_5706_serdes_has_link(struct bnx2 *bp)  in bnx2_5706_serdes_has_link()  argument
6031 	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)  in bnx2_5706_serdes_has_link()
6034 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);  in bnx2_5706_serdes_has_link()
6035 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);  in bnx2_5706_serdes_has_link()
6040 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_has_link()
6041 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6042 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6047 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);  in bnx2_5706_serdes_has_link()
6048 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6049 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6058 bnx2_5706_serdes_timer(struct bnx2 *bp)  in bnx2_5706_serdes_timer()  argument
6062 	spin_lock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6063 	if (bp->serdes_an_pending) {  in bnx2_5706_serdes_timer()
6064 		bp->serdes_an_pending--;  in bnx2_5706_serdes_timer()
6066 	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5706_serdes_timer()
6069 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6071 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6074 			if (bnx2_5706_serdes_has_link(bp)) {  in bnx2_5706_serdes_timer()
6077 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6078 				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6082 	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&  in bnx2_5706_serdes_timer()
6083 		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {  in bnx2_5706_serdes_timer()
6086 		bnx2_write_phy(bp, 0x17, 0x0f01);  in bnx2_5706_serdes_timer()
6087 		bnx2_read_phy(bp, 0x15, &phy2);  in bnx2_5706_serdes_timer()
6091 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6093 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6095 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6098 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6103 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_timer()
6104 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6105 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6107 		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {  in bnx2_5706_serdes_timer()
6108 			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {  in bnx2_5706_serdes_timer()
6109 				bnx2_5706s_force_link_dn(bp, 1);  in bnx2_5706_serdes_timer()
6110 				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_5706_serdes_timer()
6112 				bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6113 		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))  in bnx2_5706_serdes_timer()
6114 			bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6116 	spin_unlock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6120 bnx2_5708_serdes_timer(struct bnx2 *bp)  in bnx2_5708_serdes_timer()  argument
6122 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_5708_serdes_timer()
6125 	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {  in bnx2_5708_serdes_timer()
6126 		bp->serdes_an_pending = 0;  in bnx2_5708_serdes_timer()
6130 	spin_lock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6131 	if (bp->serdes_an_pending)  in bnx2_5708_serdes_timer()
6132 		bp->serdes_an_pending--;  in bnx2_5708_serdes_timer()
6133 	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5708_serdes_timer()
6136 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5708_serdes_timer()
6138 			bnx2_enable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6139 			bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;  in bnx2_5708_serdes_timer()
6141 			bnx2_disable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6142 			bp->serdes_an_pending = 2;  in bnx2_5708_serdes_timer()
6143 			bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6147 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6149 	spin_unlock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6155 	struct bnx2 *bp = (struct bnx2 *) data;  in bnx2_timer()  local
6157 	if (!netif_running(bp->dev))  in bnx2_timer()
6160 	if (atomic_read(&bp->intr_sem) != 0)  in bnx2_timer()
6163 	if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==  in bnx2_timer()
6165 		bnx2_chk_missed_msi(bp);  in bnx2_timer()
6167 	bnx2_send_heart_beat(bp);  in bnx2_timer()
6169 	bp->stats_blk->stat_FwRxDrop =  in bnx2_timer()
6170 		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);  in bnx2_timer()
6173 	if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)  in bnx2_timer()
6174 		BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6177 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_timer()
6178 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_timer()
6179 			bnx2_5706_serdes_timer(bp);  in bnx2_timer()
6181 			bnx2_5708_serdes_timer(bp);  in bnx2_timer()
6185 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_timer()
6189 bnx2_request_irq(struct bnx2 *bp)  in bnx2_request_irq()  argument
6195 	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)  in bnx2_request_irq()
6200 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_request_irq()
6201 		irq = &bp->irq_tbl[i];  in bnx2_request_irq()
6203 				 &bp->bnx2_napi[i]);  in bnx2_request_irq()
6212 __bnx2_free_irq(struct bnx2 *bp)  in __bnx2_free_irq()  argument
6217 	for (i = 0; i < bp->irq_nvecs; i++) {  in __bnx2_free_irq()
6218 		irq = &bp->irq_tbl[i];  in __bnx2_free_irq()
6220 			free_irq(irq->vector, &bp->bnx2_napi[i]);  in __bnx2_free_irq()
6226 bnx2_free_irq(struct bnx2 *bp)  in bnx2_free_irq()  argument
6229 	__bnx2_free_irq(bp);  in bnx2_free_irq()
6230 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_free_irq()
6231 		pci_disable_msi(bp->pdev);  in bnx2_free_irq()
6232 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_free_irq()
6233 		pci_disable_msix(bp->pdev);  in bnx2_free_irq()
6235 	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);  in bnx2_free_irq()
6239 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)  in bnx2_enable_msix()  argument
6243 	struct net_device *dev = bp->dev;  in bnx2_enable_msix()
6244 	const int len = sizeof(bp->irq_tbl[0].name);  in bnx2_enable_msix()
6246 	bnx2_setup_msix_tbl(bp);  in bnx2_enable_msix()
6247 	BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6248 	BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6249 	BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6253 	BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);  in bnx2_enable_msix()
6264 	total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,  in bnx2_enable_msix()
6273 	bp->irq_nvecs = msix_vecs;  in bnx2_enable_msix()
6274 	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_enable_msix()
6276 		bp->irq_tbl[i].vector = msix_ent[i].vector;  in bnx2_enable_msix()
6277 		snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);  in bnx2_enable_msix()
6278 		bp->irq_tbl[i].handler = bnx2_msi_1shot;  in bnx2_enable_msix()
6283 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)  in bnx2_setup_int_mode()  argument
6288 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6289 		msix_vecs = max(cpus + 1, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6290 	else if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6291 		msix_vecs = max(cpus, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6293 		msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6297 	bp->irq_tbl[0].handler = bnx2_interrupt;  in bnx2_setup_int_mode()
6298 	strcpy(bp->irq_tbl[0].name, bp->dev->name);  in bnx2_setup_int_mode()
6299 	bp->irq_nvecs = 1;  in bnx2_setup_int_mode()
6300 	bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6302 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)  in bnx2_setup_int_mode()
6303 		bnx2_enable_msix(bp, msix_vecs);  in bnx2_setup_int_mode()
6305 	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&  in bnx2_setup_int_mode()
6306 	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_setup_int_mode()
6307 		if (pci_enable_msi(bp->pdev) == 0) {  in bnx2_setup_int_mode()
6308 			bp->flags |= BNX2_FLAG_USING_MSI;  in bnx2_setup_int_mode()
6309 			if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_int_mode()
6310 				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_setup_int_mode()
6311 				bp->irq_tbl[0].handler = bnx2_msi_1shot;  in bnx2_setup_int_mode()
6313 				bp->irq_tbl[0].handler = bnx2_msi;  in bnx2_setup_int_mode()
6315 			bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6319 	if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6320 		bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);  in bnx2_setup_int_mode()
6322 		bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6324 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6325 		bp->num_rx_rings = bp->irq_nvecs;  in bnx2_setup_int_mode()
6327 		bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6329 	netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);  in bnx2_setup_int_mode()
6331 	return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);  in bnx2_setup_int_mode()
6338 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_open()  local
6341 	rc = bnx2_request_firmware(bp);  in bnx2_open()
6347 	bnx2_disable_int(bp);  in bnx2_open()
6349 	rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_open()
6352 	bnx2_init_napi(bp);  in bnx2_open()
6353 	bnx2_napi_enable(bp);  in bnx2_open()
6354 	rc = bnx2_alloc_mem(bp);  in bnx2_open()
6358 	rc = bnx2_request_irq(bp);  in bnx2_open()
6362 	rc = bnx2_init_nic(bp, 1);  in bnx2_open()
6366 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_open()
6368 	atomic_set(&bp->intr_sem, 0);  in bnx2_open()
6370 	memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));  in bnx2_open()
6372 	bnx2_enable_int(bp);  in bnx2_open()
6374 	if (bp->flags & BNX2_FLAG_USING_MSI) {  in bnx2_open()
6378 		if (bnx2_test_intr(bp) != 0) {  in bnx2_open()
6379 …netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report …  in bnx2_open()
6381 			bnx2_disable_int(bp);  in bnx2_open()
6382 			bnx2_free_irq(bp);  in bnx2_open()
6384 			bnx2_setup_int_mode(bp, 1);  in bnx2_open()
6386 			rc = bnx2_init_nic(bp, 0);  in bnx2_open()
6389 				rc = bnx2_request_irq(bp);  in bnx2_open()
6392 				del_timer_sync(&bp->timer);  in bnx2_open()
6395 			bnx2_enable_int(bp);  in bnx2_open()
6398 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_open()
6400 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_open()
6408 	bnx2_napi_disable(bp);  in bnx2_open()
6409 	bnx2_free_skbs(bp);  in bnx2_open()
6410 	bnx2_free_irq(bp);  in bnx2_open()
6411 	bnx2_free_mem(bp);  in bnx2_open()
6412 	bnx2_del_napi(bp);  in bnx2_open()
6413 	bnx2_release_firmware(bp);  in bnx2_open()
6420 	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);  in bnx2_reset_task()  local
6425 	if (!netif_running(bp->dev)) {  in bnx2_reset_task()
6430 	bnx2_netif_stop(bp, true);  in bnx2_reset_task()
6432 	pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);  in bnx2_reset_task()
6435 		pci_restore_state(bp->pdev);  in bnx2_reset_task()
6436 		pci_save_state(bp->pdev);  in bnx2_reset_task()
6438 	rc = bnx2_init_nic(bp, 1);  in bnx2_reset_task()
6440 		netdev_err(bp->dev, "failed to reset NIC, closing\n");  in bnx2_reset_task()
6441 		bnx2_napi_enable(bp);  in bnx2_reset_task()
6442 		dev_close(bp->dev);  in bnx2_reset_task()
6447 	atomic_set(&bp->intr_sem, 1);  in bnx2_reset_task()
6448 	bnx2_netif_start(bp, true);  in bnx2_reset_task()
6455 bnx2_dump_ftq(struct bnx2 *bp)  in bnx2_dump_ftq()  argument
6459 	struct net_device *dev = bp->dev;  in bnx2_dump_ftq()
6483 			   bnx2_reg_rd_ind(bp, ftq_arr[i].off));  in bnx2_dump_ftq()
6488 			   reg, bnx2_reg_rd_ind(bp, reg),  in bnx2_dump_ftq()
6489 			   bnx2_reg_rd_ind(bp, reg + 4),  in bnx2_dump_ftq()
6490 			   bnx2_reg_rd_ind(bp, reg + 8),  in bnx2_dump_ftq()
6491 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6492 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6493 			   bnx2_reg_rd_ind(bp, reg + 0x20));  in bnx2_dump_ftq()
6498 		   BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);  in bnx2_dump_ftq()
6503 		BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);  in bnx2_dump_ftq()
6504 		BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,  in bnx2_dump_ftq()
6506 		BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);  in bnx2_dump_ftq()
6507 		while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &  in bnx2_dump_ftq()
6511 		cid = BNX2_RD(bp, BNX2_TBDC_CID);  in bnx2_dump_ftq()
6512 		bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);  in bnx2_dump_ftq()
6513 		valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);  in bnx2_dump_ftq()
6522 bnx2_dump_state(struct bnx2 *bp)  in bnx2_dump_state()  argument
6524 	struct net_device *dev = bp->dev;  in bnx2_dump_state()
6527 	pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);  in bnx2_dump_state()
6529 		   atomic_read(&bp->intr_sem), val1);  in bnx2_dump_state()
6530 	pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);  in bnx2_dump_state()
6531 	pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);  in bnx2_dump_state()
6534 		   BNX2_RD(bp, BNX2_EMAC_TX_STATUS),  in bnx2_dump_state()
6535 		   BNX2_RD(bp, BNX2_EMAC_RX_STATUS));  in bnx2_dump_state()
6537 		   BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));  in bnx2_dump_state()
6539 		   BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));  in bnx2_dump_state()
6540 	if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_dump_state()
6542 			   BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));  in bnx2_dump_state()
6548 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_tx_timeout()  local
6550 	bnx2_dump_ftq(bp);  in bnx2_tx_timeout()
6551 	bnx2_dump_state(bp);  in bnx2_tx_timeout()
6552 	bnx2_dump_mcp_state(bp);  in bnx2_tx_timeout()
6555 	schedule_work(&bp->reset_task);  in bnx2_tx_timeout()
6565 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_start_xmit()  local
6578 	bnapi = &bp->bnx2_napi[i];  in bnx2_start_xmit()
6582 	if (unlikely(bnx2_tx_avail(bp, txr) <  in bnx2_start_xmit()
6637 	mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);  in bnx2_start_xmit()
6638 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_start_xmit()
6666 		mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,  in bnx2_start_xmit()
6668 		if (dma_mapping_error(&bp->pdev->dev, mapping))  in bnx2_start_xmit()
6689 	BNX2_WR16(bp, txr->tx_bidx_addr, prod);  in bnx2_start_xmit()
6690 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
6696 	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {  in bnx2_start_xmit()
6705 		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)  in bnx2_start_xmit()
6719 	dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6727 		dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6740 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_close()  local
6742 	bnx2_disable_int_sync(bp);  in bnx2_close()
6743 	bnx2_napi_disable(bp);  in bnx2_close()
6745 	del_timer_sync(&bp->timer);  in bnx2_close()
6746 	bnx2_shutdown_chip(bp);  in bnx2_close()
6747 	bnx2_free_irq(bp);  in bnx2_close()
6748 	bnx2_free_skbs(bp);  in bnx2_close()
6749 	bnx2_free_mem(bp);  in bnx2_close()
6750 	bnx2_del_napi(bp);  in bnx2_close()
6751 	bp->link_up = 0;  in bnx2_close()
6752 	netif_carrier_off(bp->dev);  in bnx2_close()
6757 bnx2_save_stats(struct bnx2 *bp)  in bnx2_save_stats()  argument
6759 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_save_stats()
6760 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_save_stats()
6784 	GET_64BIT_NET_STATS64(bp->stats_blk->ctr) +		\
6785 	GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6788 	(unsigned long) (bp->stats_blk->ctr +			\
6789 			 bp->temp_stats_blk->ctr)
6794 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_stats64()  local
6796 	if (bp->stats_blk == NULL)  in bnx2_get_stats64()
6843 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_get_stats64()
6844 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_stats64()
6869 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_settings()  local
6873 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_get_settings()
6876 	} else if (bp->phy_port == PORT_FIBRE)  in bnx2_get_settings()
6884 		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_get_settings()
6898 	spin_lock_bh(&bp->phy_lock);  in bnx2_get_settings()
6899 	cmd->port = bp->phy_port;  in bnx2_get_settings()
6900 	cmd->advertising = bp->advertising;  in bnx2_get_settings()
6902 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_get_settings()
6909 		ethtool_cmd_speed_set(cmd, bp->line_speed);  in bnx2_get_settings()
6910 		cmd->duplex = bp->duplex;  in bnx2_get_settings()
6911 		if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {  in bnx2_get_settings()
6912 			if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)  in bnx2_get_settings()
6922 	spin_unlock_bh(&bp->phy_lock);  in bnx2_get_settings()
6925 	cmd->phy_address = bp->phy_addr;  in bnx2_get_settings()
6933 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_settings()  local
6934 	u8 autoneg = bp->autoneg;  in bnx2_set_settings()
6935 	u8 req_duplex = bp->req_duplex;  in bnx2_set_settings()
6936 	u16 req_line_speed = bp->req_line_speed;  in bnx2_set_settings()
6937 	u32 advertising = bp->advertising;  in bnx2_set_settings()
6940 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_settings()
6945 	if (cmd->port != bp->phy_port &&  in bnx2_set_settings()
6946 	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))  in bnx2_set_settings()
6952 	if (!netif_running(dev) && cmd->port != bp->phy_port)  in bnx2_set_settings()
6979 			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_set_settings()
6990 	bp->autoneg = autoneg;  in bnx2_set_settings()
6991 	bp->advertising = advertising;  in bnx2_set_settings()
6992 	bp->req_line_speed = req_line_speed;  in bnx2_set_settings()
6993 	bp->req_duplex = req_duplex;  in bnx2_set_settings()
7000 		err = bnx2_setup_phy(bp, cmd->port);  in bnx2_set_settings()
7003 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_settings()
7011 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_drvinfo()  local
7015 	strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));  in bnx2_get_drvinfo()
7016 	strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));  in bnx2_get_drvinfo()
7032 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_regs()  local
7062 	if (!netif_running(bp->dev))  in bnx2_get_regs()
7069 		*p++ = BNX2_RD(bp, offset);  in bnx2_get_regs()
7082 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_wol()  local
7084 	if (bp->flags & BNX2_FLAG_NO_WOL) {  in bnx2_get_wol()
7090 		if (bp->wol)  in bnx2_get_wol()
7101 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_wol()  local
7107 		if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_set_wol()
7110 		bp->wol = 1;  in bnx2_set_wol()
7113 		bp->wol = 0;  in bnx2_set_wol()
7116 	device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_set_wol()
7124 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_nway_reset()  local
7130 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_nway_reset()
7134 	spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7136 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_nway_reset()
7139 		rc = bnx2_setup_remote_phy(bp, bp->phy_port);  in bnx2_nway_reset()
7140 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7145 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_nway_reset()
7146 		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_nway_reset()
7147 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7151 		spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7153 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_nway_reset()
7154 		bp->serdes_an_pending = 1;  in bnx2_nway_reset()
7155 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_nway_reset()
7158 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_nway_reset()
7160 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);  in bnx2_nway_reset()
7162 	spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7170 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link()  local
7172 	return bp->link_up;  in bnx2_get_link()
7178 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom_len()  local
7180 	if (bp->flash_info == NULL)  in bnx2_get_eeprom_len()
7183 	return (int) bp->flash_size;  in bnx2_get_eeprom_len()
7190 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom()  local
7195 	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_get_eeprom()
7204 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_eeprom()  local
7209 	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_set_eeprom()
7217 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_coalesce()  local
7221 	coal->rx_coalesce_usecs = bp->rx_ticks;  in bnx2_get_coalesce()
7222 	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;  in bnx2_get_coalesce()
7223 	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;  in bnx2_get_coalesce()
7224 	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;  in bnx2_get_coalesce()
7226 	coal->tx_coalesce_usecs = bp->tx_ticks;  in bnx2_get_coalesce()
7227 	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;  in bnx2_get_coalesce()
7228 	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;  in bnx2_get_coalesce()
7229 	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;  in bnx2_get_coalesce()
7231 	coal->stats_block_coalesce_usecs = bp->stats_ticks;  in bnx2_get_coalesce()
7239 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_coalesce()  local
7241 	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;  in bnx2_set_coalesce()
7242 	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;  in bnx2_set_coalesce()
7244 	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;  in bnx2_set_coalesce()
7245 	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7247 	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7248 	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7250 	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7251 	if (bp->rx_quick_cons_trip_int > 0xff)  in bnx2_set_coalesce()
7252 		bp->rx_quick_cons_trip_int = 0xff;  in bnx2_set_coalesce()
7254 	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;  in bnx2_set_coalesce()
7255 	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;  in bnx2_set_coalesce()
7257 	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;  in bnx2_set_coalesce()
7258 	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7260 	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7261 	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7263 	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7264 	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =  in bnx2_set_coalesce()
7267 	bp->stats_ticks = coal->stats_block_coalesce_usecs;  in bnx2_set_coalesce()
7268 	if (bp->flags & BNX2_FLAG_BROKEN_STATS) {  in bnx2_set_coalesce()
7269 		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)  in bnx2_set_coalesce()
7270 			bp->stats_ticks = USEC_PER_SEC;  in bnx2_set_coalesce()
7272 	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)  in bnx2_set_coalesce()
7273 		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7274 	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7276 	if (netif_running(bp->dev)) {  in bnx2_set_coalesce()
7277 		bnx2_netif_stop(bp, true);  in bnx2_set_coalesce()
7278 		bnx2_init_nic(bp, 0);  in bnx2_set_coalesce()
7279 		bnx2_netif_start(bp, true);  in bnx2_set_coalesce()
7288 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ringparam()  local
7293 	ering->rx_pending = bp->rx_ring_size;  in bnx2_get_ringparam()
7294 	ering->rx_jumbo_pending = bp->rx_pg_ring_size;  in bnx2_get_ringparam()
7297 	ering->tx_pending = bp->tx_ring_size;  in bnx2_get_ringparam()
7301 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)  in bnx2_change_ring_size()  argument
7303 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7305 		bnx2_save_stats(bp);  in bnx2_change_ring_size()
7307 		bnx2_netif_stop(bp, true);  in bnx2_change_ring_size()
7308 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_change_ring_size()
7310 			bnx2_free_irq(bp);  in bnx2_change_ring_size()
7311 			bnx2_del_napi(bp);  in bnx2_change_ring_size()
7313 			__bnx2_free_irq(bp);  in bnx2_change_ring_size()
7315 		bnx2_free_skbs(bp);  in bnx2_change_ring_size()
7316 		bnx2_free_mem(bp);  in bnx2_change_ring_size()
7319 	bnx2_set_rx_ring_size(bp, rx);  in bnx2_change_ring_size()
7320 	bp->tx_ring_size = tx;  in bnx2_change_ring_size()
7322 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7326 			rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_change_ring_size()
7327 			bnx2_init_napi(bp);  in bnx2_change_ring_size()
7331 			rc = bnx2_alloc_mem(bp);  in bnx2_change_ring_size()
7334 			rc = bnx2_request_irq(bp);  in bnx2_change_ring_size()
7337 			rc = bnx2_init_nic(bp, 0);  in bnx2_change_ring_size()
7340 			bnx2_napi_enable(bp);  in bnx2_change_ring_size()
7341 			dev_close(bp->dev);  in bnx2_change_ring_size()
7345 		mutex_lock(&bp->cnic_lock);  in bnx2_change_ring_size()
7347 		if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)  in bnx2_change_ring_size()
7348 			bnx2_setup_cnic_irq_info(bp);  in bnx2_change_ring_size()
7349 		mutex_unlock(&bp->cnic_lock);  in bnx2_change_ring_size()
7351 		bnx2_netif_start(bp, true);  in bnx2_change_ring_size()
7359 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_ringparam()  local
7368 	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,  in bnx2_set_ringparam()
7376 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_pauseparam()  local
7378 	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);  in bnx2_get_pauseparam()
7379 	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);  in bnx2_get_pauseparam()
7380 	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);  in bnx2_get_pauseparam()
7386 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_pauseparam()  local
7388 	bp->req_flow_ctrl = 0;  in bnx2_set_pauseparam()
7390 		bp->req_flow_ctrl |= FLOW_CTRL_RX;  in bnx2_set_pauseparam()
7392 		bp->req_flow_ctrl |= FLOW_CTRL_TX;  in bnx2_set_pauseparam()
7395 		bp->autoneg |= AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7398 		bp->autoneg &= ~AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7402 		spin_lock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7403 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_set_pauseparam()
7404 		spin_unlock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7564 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_self_test()  local
7570 		bnx2_netif_stop(bp, true);  in bnx2_self_test()
7571 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);  in bnx2_self_test()
7572 		bnx2_free_skbs(bp);  in bnx2_self_test()
7574 		if (bnx2_test_registers(bp) != 0) {  in bnx2_self_test()
7578 		if (bnx2_test_memory(bp) != 0) {  in bnx2_self_test()
7582 		if ((buf[2] = bnx2_test_loopback(bp)) != 0)  in bnx2_self_test()
7585 		if (!netif_running(bp->dev))  in bnx2_self_test()
7586 			bnx2_shutdown_chip(bp);  in bnx2_self_test()
7588 			bnx2_init_nic(bp, 1);  in bnx2_self_test()
7589 			bnx2_netif_start(bp, true);  in bnx2_self_test()
7594 			if (bp->link_up)  in bnx2_self_test()
7600 	if (bnx2_test_nvram(bp) != 0) {  in bnx2_self_test()
7604 	if (bnx2_test_intr(bp) != 0) {  in bnx2_self_test()
7609 	if (bnx2_test_link(bp) != 0) {  in bnx2_self_test()
7635 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ethtool_stats()  local
7637 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_get_ethtool_stats()
7638 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_get_ethtool_stats()
7646 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_get_ethtool_stats()
7647 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||  in bnx2_get_ethtool_stats()
7648 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||  in bnx2_get_ethtool_stats()
7649 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_ethtool_stats()
7681 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_phys_id()  local
7685 		bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_set_phys_id()
7686 		BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7690 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7699 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7703 		BNX2_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7704 		BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
7714 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_features()  local
7723 	    !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&  in bnx2_set_features()
7725 		bnx2_netif_stop(bp, false);  in bnx2_set_features()
7728 		bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);  in bnx2_set_features()
7729 		bnx2_netif_start(bp, false);  in bnx2_set_features()
7739 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_channels()  local
7743 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_get_channels()
7752 	channels->rx_count = bp->num_rx_rings;  in bnx2_get_channels()
7753 	channels->tx_count = bp->num_tx_rings;  in bnx2_get_channels()
7761 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_channels()  local
7766 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_set_channels()
7774 	bp->num_req_rx_rings = channels->rx_count;  in bnx2_set_channels()
7775 	bp->num_req_tx_rings = channels->tx_count;  in bnx2_set_channels()
7778 		rc = bnx2_change_ring_size(bp, bp->rx_ring_size,  in bnx2_set_channels()
7779 					   bp->tx_ring_size, true);  in bnx2_set_channels()
7817 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_ioctl()  local
7822 		data->phy_id = bp->phy_addr;  in bnx2_ioctl()
7828 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7834 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7835 		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);  in bnx2_ioctl()
7836 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7844 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7850 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7851 		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);  in bnx2_ioctl()
7852 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7868 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mac_addr()  local
7875 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_change_mac_addr()
7884 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mtu()  local
7891 	return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,  in bnx2_change_mtu()
7899 	struct bnx2 *bp = netdev_priv(dev);  in poll_bnx2()  local
7902 	for (i = 0; i < bp->irq_nvecs; i++) {  in poll_bnx2()
7903 		struct bnx2_irq *irq = &bp->irq_tbl[i];  in poll_bnx2()
7906 		irq->handler(irq->vector, &bp->bnx2_napi[i]);  in poll_bnx2()
7913 bnx2_get_5709_media(struct bnx2 *bp)  in bnx2_get_5709_media()  argument
7915 	u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);  in bnx2_get_5709_media()
7922 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7931 	if (bp->func == 0) {  in bnx2_get_5709_media()
7936 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7944 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7951 bnx2_get_pci_speed(struct bnx2 *bp)  in bnx2_get_pci_speed()  argument
7955 	reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);  in bnx2_get_pci_speed()
7959 		bp->flags |= BNX2_FLAG_PCIX;  in bnx2_get_pci_speed()
7961 		clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);  in bnx2_get_pci_speed()
7966 			bp->bus_speed_mhz = 133;  in bnx2_get_pci_speed()
7970 			bp->bus_speed_mhz = 100;  in bnx2_get_pci_speed()
7975 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
7980 			bp->bus_speed_mhz = 50;  in bnx2_get_pci_speed()
7986 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
7992 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
7994 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
7998 		bp->flags |= BNX2_FLAG_PCI_32BIT;  in bnx2_get_pci_speed()
8003 bnx2_read_vpd_fw_ver(struct bnx2 *bp)  in bnx2_read_vpd_fw_ver()  argument
8017 	rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,  in bnx2_read_vpd_fw_ver()
8063 	memcpy(bp->fw_version, &data[j], len);  in bnx2_read_vpd_fw_ver()
8064 	bp->fw_version[len] = ' ';  in bnx2_read_vpd_fw_ver()
8073 	struct bnx2 *bp;  in bnx2_init_board()  local
8080 	bp = netdev_priv(dev);  in bnx2_init_board()
8082 	bp->flags = 0;  in bnx2_init_board()
8083 	bp->phy_flags = 0;  in bnx2_init_board()
8085 	bp->temp_stats_blk =  in bnx2_init_board()
8088 	if (bp->temp_stats_blk == NULL) {  in bnx2_init_board()
8115 	bp->pm_cap = pdev->pm_cap;  in bnx2_init_board()
8116 	if (bp->pm_cap == 0) {  in bnx2_init_board()
8123 	bp->dev = dev;  in bnx2_init_board()
8124 	bp->pdev = pdev;  in bnx2_init_board()
8126 	spin_lock_init(&bp->phy_lock);  in bnx2_init_board()
8127 	spin_lock_init(&bp->indirect_lock);  in bnx2_init_board()
8129 	mutex_init(&bp->cnic_lock);  in bnx2_init_board()
8131 	INIT_WORK(&bp->reset_task, bnx2_reset_task);  in bnx2_init_board()
8133 	bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +  in bnx2_init_board()
8135 	if (!bp->regview) {  in bnx2_init_board()
8145 	BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8149 	bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_init_board()
8151 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_board()
8157 		bp->flags |= BNX2_FLAG_PCIE;  in bnx2_init_board()
8158 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_board()
8159 			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;  in bnx2_init_board()
8164 			bp->flags |= BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8167 		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);  in bnx2_init_board()
8168 		if (bp->pcix_cap == 0) {  in bnx2_init_board()
8174 		bp->flags |= BNX2_FLAG_BROKEN_STATS;  in bnx2_init_board()
8177 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8178 	    BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {  in bnx2_init_board()
8180 			bp->flags |= BNX2_FLAG_MSIX_CAP;  in bnx2_init_board()
8183 	if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&  in bnx2_init_board()
8184 	    BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {  in bnx2_init_board()
8186 			bp->flags |= BNX2_FLAG_MSI_CAP;  in bnx2_init_board()
8190 	if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8209 	if (!(bp->flags & BNX2_FLAG_PCIE))  in bnx2_init_board()
8210 		bnx2_get_pci_speed(bp);  in bnx2_init_board()
8213 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8214 		reg = BNX2_RD(bp, PCI_COMMAND);  in bnx2_init_board()
8216 		BNX2_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()
8217 	} else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&  in bnx2_init_board()
8218 		!(bp->flags & BNX2_FLAG_PCIX)) {  in bnx2_init_board()
8225 	bnx2_init_nvram(bp);  in bnx2_init_board()
8227 	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);  in bnx2_init_board()
8229 	if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)  in bnx2_init_board()
8230 		bp->func = 1;  in bnx2_init_board()
8234 		u32 off = bp->func << 2;  in bnx2_init_board()
8236 		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);  in bnx2_init_board()
8238 		bp->shmem_base = HOST_VIEW_SHMEM_BASE;  in bnx2_init_board()
8243 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);  in bnx2_init_board()
8252 	bnx2_read_vpd_fw_ver(bp);  in bnx2_init_board()
8254 	j = strlen(bp->fw_version);  in bnx2_init_board()
8255 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);  in bnx2_init_board()
8260 			bp->fw_version[j++] = 'b';  in bnx2_init_board()
8261 			bp->fw_version[j++] = 'c';  in bnx2_init_board()
8262 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8267 				bp->fw_version[j++] = (num / k) + '0';  in bnx2_init_board()
8272 			bp->fw_version[j++] = '.';  in bnx2_init_board()
8274 	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_init_board()
8276 		bp->wol = 1;  in bnx2_init_board()
8279 		bp->flags |= BNX2_FLAG_ASF_ENABLE;  in bnx2_init_board()
8282 			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8288 	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8292 		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);  in bnx2_init_board()
8295 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8297 			reg = bnx2_reg_rd_ind(bp, addr + i * 4);  in bnx2_init_board()
8299 			memcpy(&bp->fw_version[j], &reg, 4);  in bnx2_init_board()
8304 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);  in bnx2_init_board()
8305 	bp->mac_addr[0] = (u8) (reg >> 8);  in bnx2_init_board()
8306 	bp->mac_addr[1] = (u8) reg;  in bnx2_init_board()
8308 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);  in bnx2_init_board()
8309 	bp->mac_addr[2] = (u8) (reg >> 24);  in bnx2_init_board()
8310 	bp->mac_addr[3] = (u8) (reg >> 16);  in bnx2_init_board()
8311 	bp->mac_addr[4] = (u8) (reg >> 8);  in bnx2_init_board()
8312 	bp->mac_addr[5] = (u8) reg;  in bnx2_init_board()
8314 	bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;  in bnx2_init_board()
8315 	bnx2_set_rx_ring_size(bp, 255);  in bnx2_init_board()
8317 	bp->tx_quick_cons_trip_int = 2;  in bnx2_init_board()
8318 	bp->tx_quick_cons_trip = 20;  in bnx2_init_board()
8319 	bp->tx_ticks_int = 18;  in bnx2_init_board()
8320 	bp->tx_ticks = 80;  in bnx2_init_board()
8322 	bp->rx_quick_cons_trip_int = 2;  in bnx2_init_board()
8323 	bp->rx_quick_cons_trip = 12;  in bnx2_init_board()
8324 	bp->rx_ticks_int = 18;  in bnx2_init_board()
8325 	bp->rx_ticks = 18;  in bnx2_init_board()
8327 	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_init_board()
8329 	bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_init_board()
8331 	bp->phy_addr = 1;  in bnx2_init_board()
8334 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_board()
8335 		bnx2_get_5709_media(bp);  in bnx2_init_board()
8336 	else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)  in bnx2_init_board()
8337 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_init_board()
8339 	bp->phy_port = PORT_TP;  in bnx2_init_board()
8340 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_board()
8341 		bp->phy_port = PORT_FIBRE;  in bnx2_init_board()
8342 		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_board()
8344 			bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8345 			bp->wol = 0;  in bnx2_init_board()
8347 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {  in bnx2_init_board()
8354 				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;  in bnx2_init_board()
8356 			bp->phy_addr = 2;  in bnx2_init_board()
8358 				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;  in bnx2_init_board()
8360 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||  in bnx2_init_board()
8361 		   BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8362 		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;  in bnx2_init_board()
8363 	else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8364 		 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||  in bnx2_init_board()
8365 		  BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))  in bnx2_init_board()
8366 		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;  in bnx2_init_board()
8368 	bnx2_init_fw_cap(bp);  in bnx2_init_board()
8370 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_board()
8371 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_board()
8372 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||  in bnx2_init_board()
8373 	    !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {  in bnx2_init_board()
8374 		bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8375 		bp->wol = 0;  in bnx2_init_board()
8378 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_init_board()
8379 		device_set_wakeup_capable(&bp->pdev->dev, false);  in bnx2_init_board()
8381 		device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_init_board()
8383 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8384 		bp->tx_quick_cons_trip_int =  in bnx2_init_board()
8385 			bp->tx_quick_cons_trip;  in bnx2_init_board()
8386 		bp->tx_ticks_int = bp->tx_ticks;  in bnx2_init_board()
8387 		bp->rx_quick_cons_trip_int =  in bnx2_init_board()
8388 			bp->rx_quick_cons_trip;  in bnx2_init_board()
8389 		bp->rx_ticks_int = bp->rx_ticks;  in bnx2_init_board()
8390 		bp->comp_prod_trip_int = bp->comp_prod_trip;  in bnx2_init_board()
8391 		bp->com_ticks_int = bp->com_ticks;  in bnx2_init_board()
8392 		bp->cmd_ticks_int = bp->cmd_ticks;  in bnx2_init_board()
8405 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {  in bnx2_init_board()
8421 	bnx2_set_default_link(bp);  in bnx2_init_board()
8422 	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;  in bnx2_init_board()
8424 	init_timer(&bp->timer);  in bnx2_init_board()
8425 	bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);  in bnx2_init_board()
8426 	bp->timer.data = (unsigned long) bp;  in bnx2_init_board()
8427 	bp->timer.function = bnx2_timer;  in bnx2_init_board()
8430 	if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)  in bnx2_init_board()
8431 		bp->cnic_eth_dev.max_iscsi_conn =  in bnx2_init_board()
8432 			(bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &  in bnx2_init_board()
8434 	bp->cnic_probe = bnx2_cnic_probe;  in bnx2_init_board()
8441 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_init_board()
8443 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8446 	pci_iounmap(pdev, bp->regview);  in bnx2_init_board()
8447 	bp->regview = NULL;  in bnx2_init_board()
8460 bnx2_bus_string(struct bnx2 *bp, char *str)  in bnx2_bus_string()  argument
8464 	if (bp->flags & BNX2_FLAG_PCIE) {  in bnx2_bus_string()
8468 		if (bp->flags & BNX2_FLAG_PCIX)  in bnx2_bus_string()
8470 		if (bp->flags & BNX2_FLAG_PCI_32BIT)  in bnx2_bus_string()
8474 		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);  in bnx2_bus_string()
8480 bnx2_del_napi(struct bnx2 *bp)  in bnx2_del_napi()  argument
8484 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_del_napi()
8485 		netif_napi_del(&bp->bnx2_napi[i].napi);  in bnx2_del_napi()
8489 bnx2_init_napi(struct bnx2 *bp)  in bnx2_init_napi()  argument
8493 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_init_napi()
8494 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_init_napi()
8502 		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);  in bnx2_init_napi()
8503 		bnapi->bp = bp;  in bnx2_init_napi()
8529 	struct bnx2 *bp;  in bnx2_init_one()  local
8537 	dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);  in bnx2_init_one()
8549 	bp = netdev_priv(dev);  in bnx2_init_one()
8553 	memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);  in bnx2_init_one()
8559 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_one()
8567 	if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_init_one()
8577 		    ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',  in bnx2_init_one()
8578 		    ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),  in bnx2_init_one()
8579 		    bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),  in bnx2_init_one()
8585 	pci_iounmap(pdev, bp->regview);  in bnx2_init_one()
8597 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_remove_one()  local
8601 	del_timer_sync(&bp->timer);  in bnx2_remove_one()
8602 	cancel_work_sync(&bp->reset_task);  in bnx2_remove_one()
8604 	pci_iounmap(bp->pdev, bp->regview);  in bnx2_remove_one()
8606 	kfree(bp->temp_stats_blk);  in bnx2_remove_one()
8608 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_remove_one()
8610 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_remove_one()
8613 	bnx2_release_firmware(bp);  in bnx2_remove_one()
8627 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_suspend()  local
8630 		cancel_work_sync(&bp->reset_task);  in bnx2_suspend()
8631 		bnx2_netif_stop(bp, true);  in bnx2_suspend()
8633 		del_timer_sync(&bp->timer);  in bnx2_suspend()
8634 		bnx2_shutdown_chip(bp);  in bnx2_suspend()
8635 		__bnx2_free_irq(bp);  in bnx2_suspend()
8636 		bnx2_free_skbs(bp);  in bnx2_suspend()
8638 	bnx2_setup_wol(bp);  in bnx2_suspend()
8647 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_resume()  local
8652 	bnx2_set_power_state(bp, PCI_D0);  in bnx2_resume()
8654 	bnx2_request_irq(bp);  in bnx2_resume()
8655 	bnx2_init_nic(bp, 1);  in bnx2_resume()
8656 	bnx2_netif_start(bp, true);  in bnx2_resume()
8680 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_error_detected()  local
8691 		bnx2_netif_stop(bp, true);  in bnx2_io_error_detected()
8692 		del_timer_sync(&bp->timer);  in bnx2_io_error_detected()
8693 		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_io_error_detected()
8712 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_slot_reset()  local
8726 			err = bnx2_init_nic(bp, 1);  in bnx2_io_slot_reset()
8733 		bnx2_napi_enable(bp);  in bnx2_io_slot_reset()
8738 	if (!(bp->flags & BNX2_FLAG_AER_ENABLED))  in bnx2_io_slot_reset()
8761 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_resume()  local
8765 		bnx2_netif_start(bp, true);  in bnx2_io_resume()
8774 	struct bnx2 *bp;  in bnx2_shutdown()  local
8779 	bp = netdev_priv(dev);  in bnx2_shutdown()
8780 	if (!bp)  in bnx2_shutdown()
8785 		dev_close(bp->dev);  in bnx2_shutdown()
8788 		bnx2_set_power_state(bp, PCI_D3hot);  in bnx2_shutdown()