205 static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos)  in bnx2x_map_q_cos()  argument
208 	u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);  in bnx2x_map_q_cos()
216 		if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {  in bnx2x_map_q_cos()
218 			if (BP_PORT(bp)) {  in bnx2x_map_q_cos()
227 				BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);  in bnx2x_map_q_cos()
231 			REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);  in bnx2x_map_q_cos()
235 			reg_bit_map = REG_RD(bp, reg_addr);  in bnx2x_map_q_cos()
236 			REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));  in bnx2x_map_q_cos()
240 			reg_bit_map = REG_RD(bp, reg_addr);  in bnx2x_map_q_cos()
241 			REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);  in bnx2x_map_q_cos()
246 			if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {  in bnx2x_map_q_cos()
248 				reg_bit_map = REG_RD(bp, reg_addr);  in bnx2x_map_q_cos()
253 				REG_WR(bp, reg_addr, reg_bit_map);  in bnx2x_map_q_cos()
260 static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode,  in bnx2x_dcb_config_qm()  argument
263 	bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,  in bnx2x_dcb_config_qm()
265 	bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,  in bnx2x_dcb_config_qm()
267 	bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,  in bnx2x_dcb_config_qm()
271 		bnx2x_map_q_cos(bp, BNX2X_ETH_Q,  in bnx2x_dcb_config_qm()
273 		bnx2x_map_q_cos(bp, BNX2X_TOE_Q,  in bnx2x_dcb_config_qm()
275 		bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,  in bnx2x_dcb_config_qm()
674 static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)  in bnx2x_set_mcp_parity()  argument
680 		reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);  in bnx2x_set_mcp_parity()
687 		REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);  in bnx2x_set_mcp_parity()
691 static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)  in bnx2x_parity_reg_mask()  argument
693 	if (CHIP_IS_E1(bp))  in bnx2x_parity_reg_mask()
695 	else if (CHIP_IS_E1H(bp))  in bnx2x_parity_reg_mask()
697 	else if (CHIP_IS_E2(bp))  in bnx2x_parity_reg_mask()
703 static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)  in bnx2x_disable_blocks_parity()  argument
708 		u32 dis_mask = bnx2x_parity_reg_mask(bp, i);  in bnx2x_disable_blocks_parity()
711 			REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,  in bnx2x_disable_blocks_parity()
720 	bnx2x_set_mcp_parity(bp, false);  in bnx2x_disable_blocks_parity()
724 static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)  in bnx2x_clear_blocks_parity()  argument
734 	REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);  in bnx2x_clear_blocks_parity()
735 	REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);  in bnx2x_clear_blocks_parity()
736 	REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);  in bnx2x_clear_blocks_parity()
737 	REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);  in bnx2x_clear_blocks_parity()
740 		u32 reg_mask = bnx2x_parity_reg_mask(bp, i);  in bnx2x_clear_blocks_parity()
743 			reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].  in bnx2x_clear_blocks_parity()
754 	reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);  in bnx2x_clear_blocks_parity()
765 	REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);  in bnx2x_clear_blocks_parity()
768 static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)  in bnx2x_enable_blocks_parity()  argument
773 		u32 reg_mask = bnx2x_parity_reg_mask(bp, i);  in bnx2x_enable_blocks_parity()
776 			REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,  in bnx2x_enable_blocks_parity()
781 	bnx2x_set_mcp_parity(bp, true);  in bnx2x_enable_blocks_parity()